Answers Database

VERILOG XL: About 'Warning! Implicit wire has no fanin [Verilog-IWFA]'


Record #565

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG XL: About 'Warning!  Implicit wire has no fanin	
[Verilog-IWFA]'



Problem Description:
VERILOG XL:  'Warning!	Implicit wire xxxx has no fanin

This warning is usually caused by unconnected nets in the design.


Solution 1:

The warnings are often issued on macro pins that are not being used and can
be ignored.  It is advisable to verify this against your Verilog simulation
netlist.

If you want to drive any signal that has no fanin, add "force" statements to
your testbench .stim file.
	
For example:

	force t1.N3P_1__SUPPLY_1=1;

where t1 is the instance name of the structural Verilog model, and
N3P_1__SUPPLY_1 is the signal that has no fanin.






End of Record #565