Answers Database
XACT 5.x QuickSim: Board-level simulation for Xilinx FPGAs and CPLDs
Record #619
Product Family: Software
Product Line: Mentor
Problem Title:
XACT 5.x QuickSim: Board-level simulation for Xilinx FPGAs and CPLDs
Problem Description:
Keywords: simulation, QuickSim, board-level, Mentor
Urgency: Standard
Simulating board-level designs requires some knowledge of viewpoint
management in Mentor Graphics. Two simulation viewpoints are created, one
for functional simulation and one for timing simulation. Each Xilinx
component is then linked into the two simulation viewpoints. The way in
which each Xilinx design is linked to each top-level viewpoint depends on
whether the Xilinx component is an all-schematic FPGA; an FPGA with XBLOX,
XABEL, or XNF components; or a CPLD.
This application brief discusses the creation and management of simulation
viewpoints, as well as the importation of Xilinx-level timing information
into board-level viewpoints.
Solution 1:
GENERATING BOARD-LEVEL FUNCTIONAL AND TIMING VIEWPOINTS
In this example, assume you have the the following board-level schematic:
$CARD_XYZ/boardeaux
The following viewpoints are generated:
$CARD_XYZ/boardeaux/functional
timing
Before starting this procedure, download the following archive from the
Xilinx Download Area:
ftp://ftp.xilinx.com/pub/swhelp/mentor/boardmen_x5.tar.Z
This archive contains the scripts:
add_xilinx_func.do
add_xilinx_tim.do
regschem
getreg.nawk
unregschem
A README file is also included.
The two .do files are AMPLE scripts which add information to the
board-level simulation viewpoints for functional and timing simulation.
The REGSCHEM and GETREG scripts register the simulation models created by
Fncsim8 and Timsim8 to your original component so that they may referenced
by your functional and timing viewpoints. The last utility, UNREGSCHEM,
lets you quickly unregister schematic models in case of misregistration.
Once these files are extracted, proceed with the following steps.
1. Invoke the stand-alone Design Viewpoint Editor from the command line:
dve
2. To create a functional viewpoint, select OPEN VPT from the DVE Palette
and in the dialog box enter:
Component name: $CARD_XYZ/boardeaux
Viewpoint: functional
3. Enter the viewpoint information required for the non-Xilinx components
in the design, if any. See the vendor who supplied you the non-Xilinx
simulation models for more details.
4. Run within DVE the add_xilinx_func.do script you downloaded from the
Xilinx FTP site, by typing in:
dofile add_xilinx_func.do
(A command pop-up will apear as you start typing.)
This script writes Xilinx-specific properties into the board-level
viewpoint. In addition, it includes the following setting:
$add_parameter("lca_simtype", "functional", @string);
The lca_simtype parameter allows Xilinx components to be changed easily
from functional to timing models in Quicksim by simply changing which
viewpoint is fed into the simulator.
Save the design viewpoint by selecting the SAVE VPT button in the DVE
Palette.
5. Repeat Steps 2-4 for a new viewpoint. This time, when you do OPEN VPT,
type in the following information:
Component name: $CARD_XYZ/boardeaux
Viewpoint: timing
Now run the timing viewpoint script, add_xilinx_tim.do:
dofile add_xilinx_tim.do
6. Exit DVE.
Note: If you already have functional and timing viewpoints set up for your
board-level simulations, use these instead when entering the information in
Step 2.
7. Follow the instructions in Resolutions 2 through 4 to import each Xilinx
component into the board-level viewpoints for simulation. Each of these
resolutions describes a specific methodology for importation based on
whether the component is an FPGA (with or without XBLOX) or a CPLD.
8. To run a particular simulation on the design, specify the VIEWPOINT name
on the Quicksim command line, rather than just the component name. For
example, to run a functional simulation:
quicksim boardeaux/functional -tim unit
To run a timing simulation:
quicksim boardeaux/timing -tim typ
As explained in the following resolutions, the correct Xilinx models (for
functional or timing simulation) are automatically pulled into Quicksim
based on the value of the lca_simtype parameter.
Note: There is currently no way to independently reset Xilinx components in
Quicksim. All XC2000 and XC3000 devices must share a common //globalresetb
signal, all XC4000 devices must share a common //globalsetreset signal, all
XC5200 devices must share a common //globalreset signal, and all XC7000
devices most share a common //prld signal.
Solution 2:
IMPORTING AN FPGA DESIGN THAT DOES NOT CONTAIN XBLOX, XABEL, OR XNF MODULES
Assume you have the following Xilinx component:
$CARD_XYZ/xilinx/proc/processor: XC5200 design
(instance name: SEQUENCER)
1. Attach these properties to the FPGA instance in the boardeaux schematic:
NAME VALUE TYPE
lca_technology xc5200 string
MODEL default string
(These may also be made body properties on the symbols themselves.)
TO PREPARE FOR FUNCTIONAL SIMULATION
There is nothing else to do; all models have now been set up. Quicksim
only needs to read in the original schematic design to simulate the system
properly.
You are now ready to run Quicksim for functional as in Resolution 1.
TO PREPARE FOR TIMING SIMULATION
Step 2 (and only Step 2) will need to be rerun on the FPGA design whenever
this part of the design is modified.
2. After the design has been placed and routed by the FPGA tools, run
Timsim8 with the -o (use original) option, e.g.:
timsim8 processor -o
This generates a .mba (Mentor back-annotation) file, which will be
imported into the board-level simulation viewpoint in the next step.
3. Invoke DVE as before, then open the TIMING board-level viewpoint
(Component: $CARD_XYZ/boardeaux, Viewpoint: timing).
4. Select File -> Back Annotation -> Import... and enter the following
information in the dialog box:
Ascii BA File: $CARD_XYZ/xilinx/proc/processor.mba
BA Name: $CARD_XYZ/boardeaux/timing/sequencer
Import Context: /SEQUENCER (the instance name of the symbol)
5. Save the viewpoint and close DVE.
You are now ready to run Quicksim for timing as in Resolution 1.
Solution 3:
IMPORTING AN FPGA DESIGN THAT CONTAINS XBLOX, XABEL, OR XNF MODULES
Assume you have the following Xilinx component:
$CARD_XYZ/xilinx/dsp/dsp_filter: XC4000E XBLOX design
(instance name: FILTER)
To prevent "collision" of the simdir directories that Fncsim8 creates, each
XBLOX FPGA design must be placed in its own directory. This is why there
is a directory underneath $CARD_XYZ/xilinx where the component is located.
(If you had another XBLOX design, for example, you may have put it in
$CARD_XYZ/xilinx/tube/tube_screen.) Also, Xilinx recommends that all input
and output pads reside on the top level of an FPGA design; no INPUTS,
OUTPUTS, or BIDIR_IO symbols should be used.
1. Attach these properties to the FPGA instance in the boardeaux schematic:
NAME VALUE TYPE
lca_technology xc4000e string
MODEL lca_simtype expression
(These may also be made body properties on the symbols themselves.)
Note the MODEL property, which is used to swap between functional and
timing models. Setting this property to be of type EXPRESSION (instead
of STRING) allows this property to be changed dynamically, as seen by
Quicksim, by simply telling the simulator which viewpoint to use.
TO PREPARE FOR FUNCTIONAL SIMULATION
Step 2 (and only Step 2) will need to be rerun on the FPGA design whenever
this part of the design is modified.
2. Run Men2XNF8 and Fncsim8 -o on the dsp_filter design as normal.
men2xnf8 -p 4013ehq240-4 dsp_filter
fncsim dsp_filter -o
This creates the functional model $CARD_XYZ/dsp/simdir/dsp_filter.
3. Use the Component Interface Browser to add this new model to the model
registry of the FPGA component. You can do this with the REGSCHEM
script supplied in the boardmen.tar.Z archive:
regschem -f dsp_filter simdir/dsp_filter/schematic
(You may leave off the "/schematic" if you wish.)
After you run REGSCHEM, you can look at the cib_view.log file and see a
listing structured like the following:
** view
COMPONENT dsp_filter DEFAULT INTERFACE IS: dsp_filter
INTERFACE: dsp_filter
PINS:
(list of pins)
BODY PROPERTIES: (list)
INTERFACE MODEL ENTRIES:
Model Entry Type Model Info
(list)
Note that there may be more than one INTERFACE line; the interface you
care about is the one named in the DEFAULT INTERFACE field.
At the bottom of the interface description, you will see the following:
0 mgc_symbol Path: $CARD_XYZ/dsp/dsp_filter/dsp_filter
Labels: 'default_sym'
Status: Valid for interface; Valid for property
1 mgc_schematic Path: $CARD_XYZ/dsp/dsp_filter/schematic
Labels: '$schematic' 'schematic' 'default'
Status: NOT valid for interface; NOT valid for property
2 mgc_schematic Path: $CARD_XYZ/dsp/simdir/dsp_filter/schematic
Labels: '$schematic' 'schematic' 'functional'
Status: NOT valid for interface; NOT valid for property
Model entry 2 has been added by the the REGSCHEM command with a label of
"functional."
The model you have registered will be accessible by any instantiation of
this instance which has a MODEL=functional property attached to it.
When you tell Quicksim to run on the functional viewpoint, the parameter
lca_simtype=functional changes the MODEL=lca_simtype(exp) to become
MODEL=functional as seen by Quicksim. Quicksim then pulls in the newly
registered model whose label is "functional", which is how you labeled
the model that Fncsim8 generated.
You are now ready to run Quicksim for functional as in Resolution 1.
TO PREPARE FOR TIMING SIMULATION
Step 4 (and only Step 4) will need to be rerun on the FPGA design whenever
this part of the design is modified.
4. After the design has been placed and routed by the FPGA tools, run
Timsim8 with the -g (auto-generate) option, e.g.:
timsim8 dsp_filter -g
This generates a $CARD_XYZ/xilinx/dsp/dsp_filter_tim netlist with timing
information.
5. Register this model with the original component in CIB as before, but
instead of using the -f option in REGSCHEM, use the -t option:
regschem -t dsp_filter dsp_filter_tim/schematic
The cib_view.log file will now show:
3 mgc_schematic Path: $CARD_XYZ/xilinx/dsp/dsp_filter_tim/schematic
Labels: '$schematic' 'schematic' 'timing'
Status: NOT valid for interface; NOT valid for property
The model you have registered will be accessible by any instantiation of
this instance which has a MODEL=timing property attached to it. When
you tell Quicksim to run on the timing viewpoint, the parameter
lca_simtype=timing changes the MODEL=lca_simtype(exp) to become
MODEL=timing as seen by Quicksim. Quicksim then pulls in the newly
registered model whose label is "timing", which is how you labeled the
model that Timsim8 generated.
You are now ready to run Quicksim for timing as in Resolution 1.
Solution 4:
IMPORTING A CPLD DESIGN
Assume you have the following Xilinx component:
$CARD_XYZ/xilinx/ifc/if_control: XC7300 design
(instance name: CONTROLLER)
1. Attach these properties to the FPGA instance in the boardeaux schematic:
NAME VALUE TYPE
lca_technology xc7000 string
MODEL lca_simtype expression
(These may also be made body properties on the symbols themselves.)
Note the MODEL property, which is used to swap between functional and
timing models. Setting this property to be of type EXPRESSION (instead
of STRING) allows this property to be changed dynamically, as seen by
Quicksim, by simply telling the simulator which viewpoint to use.
TO PREPARE FOR FUNCTIONAL SIMULATION
Although Fncsim8 does not need to be run to generate a functional model,
CPLDs still use a different model for timing simulation. Therefore, as in
Resolution 3, the original schematic must be labeled "functional" so that
it may be swapped for the delay model during timing simulation in Quicksim.
2. Use the Component Interface Browser to add a "functional" label to the
original schematic model. You can do this using the REGSCHEM script:
regschem -f if_control if_control/schematic
(You may leave off the "/schematic" if you wish.)
After you run REGSCHEM, you can look at the cib_view.log file and see a
listing structured like the following:
** view
COMPONENT if_control DEFAULT INTERFACE IS: if_control
INTERFACE: if_control
PINS:
(list of pins)
BODY PROPERTIES: (list)
INTERFACE MODEL ENTRIES:
Model Entry Type Model Info
(list)
Note that there may be more than one INTERFACE line, the interface we
care about is the one named in the DEFAULT INTERFACE field.
At the bottom of the interface description, you will see the following:
0 mgc_symbol Path: $CARD_XYZ/ifc/if_control/if_control
Labels: 'default_sym'
Status: Valid for interface; Valid for property
1 mgc_schematic Path: $CARD_XYZ/ifc/if_control/schematic
Labels: '$schematic' 'schematic' 'default' 'functional'
Status: NOT valid for interface; NOT valid for property
REGSCHEM has added a "functional" label to the original schematic model.
The model we have labeled will be accessible by any instantiation of
this instance which has a MODEL=functional property attached to it.
When you tell Quicksim to run on the functional viewpoint, the parameter
lca_simtype=functional changes the MODEL=lca_simtype(exp) to become
MODEL=functional as seen by Quicksim. Quicksim then pulls in the
original schematic, which now has a label of "functional".
You are now ready to run Quicksim for timing as in Resolution 1.
TO PREPARE FOR TIMING SIMULATION
Step 3 (and only Step 3) will need to be rerun on the FPGA design whenever
this part of the design is modified.
3. After the design has been implemented by the CPLD tools, run Timsim8
with the -g (auto-generate) option.
timsim8 if_control -g
This generates a $CARD_XYZ/xilinx/ifc/if_control_tim netlist with timing
information.
4. Register this model with the original component in CIB as before, but
instead of using the -f option in REGSCHEM, use the -t option:
regschem -t if_control if_control_tim/schematic
The cib_view.log file will now show:
2 mgc_schematic Path: $CARD_XYZ/xilinx/ifc/if_control_tim/schematic
Labels: '$schematic' 'schematic' 'timing'
Status: NOT valid for interface; NOT valid for property
The model you have registered will be accessible by any instantiation of
this instance which has a MODEL=timing property attached to it. When
you tell Quicksim to run on the timing viewpoint, the parameter
lca_simtype=timing changes the MODEL=lca_simtype(exp) to become
MODEL=timing as seen by Quicksim. Quicksim then pulls in the newly
registered model whose label is "timing", which is how you labeled the
model that Timsim8 generated.
You are now ready to run Quicksim for timing as in Resolution 1.
End of Record #619
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