Answers Database

VERILOG-XL: How to handle upper/lower case conversion of Verilog signalnames


Record #627

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG-XL:  How to handle upper/lower case conversion of Verilog
signalnames



Problem Description:
Keywords: verilog upper lower case

Urgency:  standard

General Description:

Users may find that the Verilog-XL simulator is unable to
recognize signal names that they declare in their original,
Verilog behavioral description and test bench files when they
attempt to simulate their designs AFTER synthesizing them.

One of the reasons for this is because the case of the signal
and instantiated library component names in the original
testbench file do not match those in the synthesized design netlist.

The problem is often seen in designs done in Synopsys, when
the user declares signal names in lower case in the original
Verilog source description.  The Synopsys tools, SYN2XNF, and
XNFMERGE all preserve the case of signal names.  However, if
Synopsys happens to target X-BLOX modules in the design,
X-BLOX will convert the lower case names to upper case in the
resulting netlist.  The upper case names are preserved for the
remainder of the implementation process, all the way
up to the generation of the Verilog functional or timing
simulation netlist.

As a result, if the user tries to use the same test bench for
post-synthesis simulation that he/she used for behavioral
simulation, and this test bench has signals declared all in
lower case, Verilog will not recognize any of the signals and
symbol names in the testbench because of its case-sensitive
nature.


Solution 1:


The best solution is to use only UPPER CASE for signal and
instance names in the behavioral Verilog netlist from the
start to avoid these types of problems.

If a design already contains mixed case or lower case names, a
workaround is to use the following Unix command to make the
case of all names consistent:

	>dd conv={ucase,lcase} < {input file} > {output file}

Example:  To convert all uppercase names to lowercase:

	>dd conv=lcase < oldfile.v > newfile.v

where oldfile.v is the input file and newfile.v is the output
file.  For timing simulation, you will need to convert the
.sdf file also to match up all instance names in the design.





End of Record #627