Answers Database

CADENCE VERILOG-XL: driving GSR, GR (global reset) and GTS in Verilog simulation.


Record #646

Product Family:  Software

Product Line:  Cadence

Problem Title:
CADENCE VERILOG-XL: driving GSR, GR (global reset) and GTS in Verilog
simulation.



Problem Description:
Keywords: gsr gr gts verilog global reset tristate

Urgency: standard

General description:
How to drive GSR, GR and GTS in Verilog simulation.



Solution 1:


GSR, GR, and GTS are defined as wires at the bottom of the .v
Verilog source file generated by XNF2Verilog or XNF2CDS for a
design in a module called <design>_globals.

These signals are buried and not hooked up at the chip level
(i.e., they will not appear in the main module port
declaration).  Instead, they are declared as wires in a
separate global module within the .v file.

To drive these signals in a Verilog simulation, you need to
use the FORCE command, and the signals must be referenced as
<module>.<signal_name>:

	force  <design_name>_globals.[gsr, gr, gts] = [0,1];

	Example:

	force calct_globals.gsr=1;

Here, calct_globals is the name of the global module, which is
declared in the .v file generated by XNF2VERILOG/XNF2CDS.
calct is the design name, and the global signal being driven
is GSR.





End of Record #646