Answers Database

CADENCE VERILOG-XL: Buffer output does not follow transitions on its input (transport and inertial delays)


Record #648

Product Family:  Software

Product Line:  Cadence

Problem Title:
CADENCE VERILOG-XL:   Buffer output does not follow transitions on its
input (transport and inertial delays)



Problem Description:
Keywords:  gclk clock buffer verilog follow transport delay
inertial, pulse swallowing

Urgency: standard

General Description:
GCLK or other clock buffer's output does not follow
transitions on its input during simulation.  The buffer
output ends up being stuck at 0 or stuck at 1.

VERSION:  Verilog-XL version 2.1 and above

This is usually due to the user trying to clock the design at
a higher rate than allowed, based on the delay between the
I/O pin and the clock buffer output.

Verilog-XL runs in "pulse swallowing mode" by default, which
means that it will simulate distributed delays as *inertial
delays* unless told to do otherwise.  With an inertial delay,
a delaying element does not pass a pulse through if its
duration is shorter than the element's delay to its output.

On the other hand, an element with *transport delay*
functionality *does* pass pulses of shorter duration than the
element's delay.





Solution 1:


Force Verilog-XL v2.1 and higher to enable transport delay
functionality by using the following options when invoking
the Verilog simulation:
	
	     +transport_path_delays  (Enables transport delay
			 	functionality and pulse
				control for module path
				delays.)

	     +transport_int_delays  (this option enables
				transport delay functionality
				and pulse control for inter-
				connect delays.)

	     +multisource_int_delay  (Enables transport delay
				functionality and pulse
				control for interconnect
				delays plus unique source-
				load delays for multi-
				source nets.)

For Verilog-XL v2.5, pulse you may also need to specify these
additional pulse limit options:

	     +pulse_e/n

	     Example:

	     +pulse_e/0      sets the module output path to e
				(error state) and lets the
				module path output pulse pass
				through if the pulse width
				exceeds 0 time units)



	     +pulse_r/m  (sets the module output path to e
				(error state) and lets the
				module path output pulse pass
				through if the pulse width
				exceeds 0 time units)

Also in Verilog-XL v2.5, interconnect delays are controlled
with the following plus options on the command line:

	    +pulse_int_e/n
	    +pulse_int_r/m

(See the 97A Verilog-XL Reference Manual, Chapter 12, p.24,
for more details)

You can determine whether routing and component delays are
the cause of the problem by using XDelay to run a static
timing analysis on the problem path to check the delay of the
buffer input signal against the delay through the buffer.
		




End of Record #648