Answers Database

Xdelay/Timing Analyzer 6.0: Reported Setup Value on Carry Logic Path appears erroneous


Record #672

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
Xdelay/Timing Analyzer 6.0: Reported Setup Value on Carry Logic Path
appears erroneous



Problem Description:
It is possible for XDelay and Timing Analyzer to report setup delays
along a carry logic path which appear to be larger than the guranteed
values in the Data Book.  An example is a carry-in (CIN) signal which
enters a CLB on the F1 pin and feeds the CLB flip-flop data pin.  The
Data Book indicates that the setup time from F/G inputs should be
4.5nS (Tick).  However, in this example, XDelay and Timing Analyzer
reports a setup time of 9.5nS:

Thru: Net SA6		       to CLB_R3C4.F1	 :    1.7ns ( 22.9ns)
  To: FF Setup (D), Blk Q6			 :    9.5ns ( 32.4ns)


Solution 1:

The Tick value of 4.5nS indicated in the Data Book refers to the setup
time from an F pin to FFX, or from a G pin to FFY.  However, the 9.5nS
value reported refers to the setup time from the F1 pin, through the
carry-logic generator, through the G function generator, to FFY.
Although XDelay and Timing Analyzer does not report the details of this
path, the reported setup value is accurate (9.5nS in this example).




End of Record #672