Answers Database

PPR 5.2.0 issues error 5846 on designs where the aclk or gclk is fed from a clb and the clb location is constrained


Record #694

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
PPR 5.2.0 issues error 5846 on designs where the aclk or gclk is fed
from a clb and the clb location is constrained



Problem Description:
PPR 5.2.0 may issue this error on a legally constrained design:
  *** PPR: ERROR 5846:
	    The ACLK symbol `global buffer
	    '/$1I274/$1I312/$1I634' (type=ACLK, output
	    signal=/RCVCLK)' is sourced directly from the pad
	    signal `/$1I274/$1I312/RVCLK' and must use the
	    dedicated pad. However, it has been constrained to a non-dedicated
	    location. Correct or remove the constraint (no constraint is
	    necessary since only one location is possible).

The constrain that causes this is on a clb that feeds the aclk:
PLACE BLOCK /$1I274/$1I312/RVCLK: QN; This happens with either the
aclk or the gclk.


Solution 1:

This problem arises because PPR  fails to check the source of the aclk or gclk b
ut does check the constraints on the source. There are several workarounds:

1. Don't constrain this location. The floorplanner will automatically write out
a constraint for this if the block is floorplanned.  Edit the <design>.cst file
and remove the constraint.

2. Constrain the block to only one possible location using a NOTPLACE BLOCK cons
traint.
    Use the following syntax:

    NOTPLACE BLOCK /$1I274/$1I312/RVCLK: [AA PP] [QA TM] [QO TP] [RN TN];

    Notice that this blocks out the four regions around the desired location (QN
); by default
    the block will be place in the correct location (QN)

3. Use version 5.1.0 of PPR. This problem doesn't appear in that version.



End of Record #694