Answers Database

Decoupling Capacitors


Record #777

Product Family:  Hardware

Product Line:  4000

Problem Title:
Decoupling Capacitors


Problem Description:
Recommendations for an "optimal way to decouple Xilinx devices.


Solution 1:

The standard Vcc-decoupling rule for modern CMOS -ICs is to mount one
low-inductance decoupling capacitor of 0.01 to 0.1 uF very close to each Vcc
pin. The purpose of these decoupling capacitors is to provide the fast changing
dynamic supply current, especially when capacitively loaded outputs are
switching.
The big power-supply capacitor, and even the 100uF  board-decoupling capacitor
cannot perform this function for two reasons: Those big capacitors have an
unavoidable internal series-inductance which makes them incapable of supplying
fast-changing current pulses with nanosecond rise and fall-times.
These capacitors are also physically too far away from the devices that need
access to an instant current reservoir. Even a good power/ground-distribution
network has unacceptable inductance over distances of several inches.
As CMOS devices have become faster and as the number of outputs increases, good
decoupling is becoming more important. Current pulses with 1 ns rise or
fall-time must be treated like GHz signals, and the digital pc-board designer
might learn something from looking inside a UHF-TV tuner.
Here are some quantitative data:
Let us assume a device with 40 outputs switching simultaneously ( or within a
few nanoseconds of each other ), with each output driving a 100 pF load. With
an output swing of 4 V and all outputs switching in the same direction, each
such transition consumes 0.016 uCoulomb.
If four decoupling capacitors of 0.01 uF have to supply this charge, they will
drop their voltage by 0.016/0.04 = 0.4 V .
That is barely acceptable, and four 0.1 uF decoupling capacitors would be
preferred, since they reduce this drop by an order of magnitude.
Capacitors larger than 0.1 uF tend to have more internal series-inductance, so
they are actually inferior for this application.

Another way to look at dynamic current requirements is to start with power
dissipation:
A 3-W device clocked at 40 MHz does not consume a steady 600 mA, but might
consume 3 A for 5 ns, and very little for the rest of the time.
As explained above, these 0.015 uCoulomb require at least four 0.1 uF
decoupling capacitors, and 0.1 uF would be better.

The need for Vcc decoupling varies with the amount of internal logic, and the
number of outputs switching ( worst-case ) simultaneously, and their capacitive
load. The classical rule of one low-inductance 0.01 to 0.1 uF at each Vcc pin
is still a good guideline.



End of Record #777