Answers Database

Post-synthesis Verilog-XL functional simulation is not supported by FUNCNET/FUNCNETX in Cadence and ES-Verilog interface, or in Xilinx M1.3


Record #806

Product Family:  Software

Product Line:  Cadence

Problem Title:
Post-synthesis Verilog-XL functional simulation is not supported by
FUNCNET/FUNCNETX in Cadence and ES-Verilog interface, or in Xilinx M1.3



Problem Description:
Keywords:  post-synthesis functional simulation synopsys,
xact, xnf2verilog, ngd2ver, M1, funcnet

Urgency:  standard

General Description:
Post-synthesis functional simulation of Synopsys designs as
well as other third party synthesis tools is
currently not supported by the 5.1.1 or 5.2.x ES-Verilog
Interface and Libraries, by the Verilog interface shipped by
Cadence (9404 through 97B), or by the Xilinx M1.3 Alliance
Series release.

The only current exception is the output of the Cadence
Synergy tool in the Cadence 97B release (contact Cadence
for details).


XACT 5 Flow:

Problems with this flow include resolution of certain symbols
found in a post-synthesis XNF netlist processed by SYN2XNF,
including symbols with SCHNM properties that do not reference
Unified library simulation primitives (FDC, FDP, BUFGP_F,
etc.).	For example, SCHNM=FDC references an FDC flipflop,
which is not a valid Unified library simulation
primitive.  The correct Unified primitive would be an FDCE.

Since XNF2CDS and XNF2VERILOG key off the SCHNM property when
they translate the XNF file to Verilog, and the libraries only
support Unified library primitives, the translation will fail.

The second issue is with SYM records that are missing SCHNM
properties completely.	These may arise if Synopsys targets
XBLOX modules in the design for certain functions.  The SYM
records for such modules will lack SCHNM properties
altogether. In versions of XNF2CDS and XNF2VERILOG
prior to version 9504-1.30v, this situation would result in a
processing failure.


M1 Flow:

The main problem is with unsupported primitives written
out by the M1.3 Synopsys interface in the M1 flow--for
example, FDC, FDP, BUFGP_F.


Solution 1:

XACT 5.x flow:

The workaround is to run XMAKE -x -n on the design.xnf to
generate an XTF file, then run PPR with placer_effort=1 and
route=false options to get a mapped .LCA file.	Finally run
TIMENET or TIMENETX -x to generate the simulation netlist
without running XNFBA, and specify the +delay_mode_unit
when running Verilog-XL to run a unit delay simulation.

xmake -x -n design
ppr design placer_effort=1 route=false
timenet -x design
verilog +delay_mode_unit designt.v designt.stim

Note that it is critical to specify the -x option in
TIMENET/TIMENETX so that XNFBA does not restore the original
SCHNM properties.



Solution 2:

XACT 5.x flow:

If the problem is only with the following components
in the design:

  FDC
  FDP
  IFD
  OFD
  OFDT
  BUFGP_F

You can process the design if you strip out the SCHNM
properties associated with these symbols in the .xff output of
SYN2XNF, since in the absence of SCHNM properties on a SYM
record in the XNF/XFF file, XNF2CDS and XNF2VERILOG 9504-1.30v
or later will resolve the symbol to the correct simulation
primitive.

If you choose to pursue this route, you must be sure to
explicitly specify the .xff file out of SYN2XNF after the
SCHNM properties have been stripped out as the input to
funcnet.

Example:   funcnet design.xff 4000




Solution 3:

M1 flow:

Process the .SXNF through NGDBUILD, then run NGD2VER to
generate a post-NGDBUILD Verilog netlist for simulation,
being sure to specify a different name for the output
netlist so that you do not overwrite the original .v file:

   ngdbuild design_name
   ngd2ver -ul -tf design_name design_name_ps



End of Record #806