Answers Database
CONCEPT: How to do block mode designs (build symbols, integrate XNF files) into a schematic, chips_prt or schematic not found
Record #807
Product Family: Software
Product Line: Cadence
Problem Title:
CONCEPT: How to do block mode designs (build symbols, integrate XNF
files) into a schematic, chips_prt or schematic not found
Problem Description:
How to do block mode designs (build symbols, integrate XNF files) into a schemat
ic
VERSIONS: applies to Concept 1.7 or later, 9404 Cadence release or later
Related ERROR MESSAGES:
chips_prt not found for block, or no schematic found for
block
Solution 1:
If you are using Concept in conjunction with FPGA Designer:
-----------------------------------------------------------
In the 9404 and 9502 online Xilinx Interface to Concept User Guide, refer
to the section on doing block mode designs in Concept on
p.2-20. This section describes using FUNCNET to generate the
symbol for a non-schematic block using the -body option from your
XNF file.
Syntax: funcnet <design_name> <architecture> -body -sim -r <run_dir> -o
<design_name>
Example: funcnet rom_mem 4000 -body -sim -r . -o rom_mem
The above applies to XNF blocks generated by a Cadence tool (from a Concept or
Composer schematic, or from the Cadence synthesis tool, Synergy)
If you are using the SCALD methodology:
1. Connectivity between the symbol and the underlying schematic is established
by appending a \I to the end of each I/O signal that corresponds to the upper
level symbol pin.
2. In addition, FLAG bodies must be attached to the interface
signals to indicate signal directions.
NOTE: If the XNF file originates from some other third party vendor, this may no
t work.
If you are using Synergy and Concept with FPGA Designer and have a Verilog/VHDL
block:
-------------------------------------------------------------------------------
You can use the GENVIEW command to generate a body. For you to do this, you
must enable HDL_Direct mode by adding the following lines to
your startup.concept file:
set_hdl_direct on
set_hdl_checks on
set check_ok_hdl_net_names on
set check_ok_hdl_port_names on
set check_signames on
The command is:
genview body vhdl (this is invoked from within Concept after you
open
the design in question for editin
g)
Refer to the online Xilinx FPGA Designer (Concept) User Guide, Ch.2, p. 8.
If the XNF file originates from some other third party vendor:
--------------------------------------------------------------
Manually create a "parts" file (part_cn) for the block by typing the
following in Concept:
1."edit foo.part" to create a part drawing for the block
called "foo"
2. "add drawing" to add a drawing body to this part
drawing
3. "attr" to activate adding attributes
4. Select the drawing body and add these two properties to the part
drawing:
ABBREV = foo
TITLE= <block_description>
The value of TITLE should be a descriptive title for the block.
5. do a "write" to save the part drawing.
ALSO:
You will also need to build a symbol body for the XNF block manually if
you are coming from a third party-generated XNF. To do this, type:
edit foo.body
If you are using the SCALD methodology, as opposed to making it
HDL_Direct compliant), you will also need to add the
property, INPUT_LOAD=*,* to each *input* pin on the symbol. so that the
the direction of the pin in the XNF file's PIN record will be written
out correctly. Type:
1. "pr" to activate adding properties
2. click on an input pin to select it. This causes a rectangular
box to appear.
3. type "INPUT_LOAD=*,*" and hit return. (properties must be entered
as "name=value" pairs, and *,* is entered as a dummy value)
4. move the box to where you want the property to appear on the
page and click again to put it in that location
5. type "sh pr" to display all the properties on the symbol to
verify that you have done this properly.
The design is then ready to for processing by concept2xnf.
Note that adding the FILE= attribute to the symbol body is no longer needed for
XNF blocks.
End of Record #807
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |