Answers Database
Mentor/PLD_DA 5.2: Convert Design loses NET, LOC, other port properties
Record #822
Product Family: Software
Product Line: Mentor
Problem Title:
Mentor/PLD_DA 5.2: Convert Design loses NET, LOC, other port properties
Problem Description:
Keywords: Convert Design, NET, LOC, PAD, properties, Design Architect
Urgency: Standard
General Description:
(For more information on Convert Design, see Solution 798, "Retargeting a
design in Mentor Design Architect.")
Convert Design may lose NET, LOC, and other properties associated with
schematic ports or PADs in a Mentor design. This problem is known to
happen in Mentor A.3-F (8.4_3) and above but not in Mentor A.1-F (8.4_1).
It is unknown what behavior occurs in A.2.
Solution 1:
The $LCA/des_arch/da_session.ample script controls, among other things, the
behavior of Convert Design. A script is available that replaces this AMPLE
AMPLE file with one that will make Convert Design behave properly under the late
r
versions of Mentor. You can download this fix from the File Download Area:
ftp://ftp.xilinx.com/pub/swhelp/mentor/cvtdsgn_fix.tar.Z
End of Record #822
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |