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Synopsys: XC5200: clock inversion is implemented in a function generator, not at the flip-flop.


Record #857

Product Family:  Software

Product Line:  Synopsys

Problem Title:
Synopsys: XC5200: clock inversion is implemented in a function
generator, not at the flip-flop.



Problem Description:
When Synopsys performs mapping for 5200 designs, the "replace_fpga" command is n
ot required.  Instead of writing to gates, the compiler writes EQN records in th
e .sxnf file to map combinatorial logic to function generators.  This means that
 simple inversions or events on the negative clock-edge in your code result not
in an INV record in the .sxnf, but rather in an EQN record with the equation's b
eing equal to ~I0.

Since the Xilinx tools do not see this as an absorbable inverter, it is placed i
n a separate function generator (just as the EQN statement mandates).  Thus the
clock inversion for flip-flops triggered on the negative edge of the clock takes
 place in a separate Logic Cell, rather than directly at the flip-flop's clock p
in.


Solution 1:

Either of the solutions below will work:

1.  After compiling in Synopsys, run the command "replace_fpga -force".  This wi
ll put everything in terms of gates.  You will lose all of Synopsys' mapping dir
ectives, leaving all mapping up to the Xilinx core tools.  Do this before writin
g out the .sxnf file.

-OR-

2.  Manually edit the .xff file, deleting the offending EQN component(s)
and modifying the appropriate PIN records to include an INV attribute.
This is really only a solution for specific cases
such as an inverted GSR pin to STARTUP or a negative edge clock.

Below is an example of a falling-edge-clocked flip-flop correctly written in XNF
 format:
SYM, out_reg/$1I13, DFF, HIERG=2, LIBVER=2.0.0
PIN, C, I, n34, , INV
PIN, D, I, n33
PIN, Q, O, n32





End of Record #857