Answers Database
PPR 5.20: Support for dual phase clocks in 3000A devices
Record #945
Product Family: Software
Product Line: FPGA Core
Problem Title:
PPR 5.20: Support for dual phase clocks in 3000A devices
Problem Description:
Dual phase clocking is supported by PPR 5.0 and later
for XC3000A devices, but not by APR for XC3000 devices.
It is highly recommended that the clock signal in this
situation be sourced by the ACLK buffer.
Using GCLK is not an option because it cannot connect
to both of the clock lines on an XC3000/XC3000A die edge.
If no clock buffer is used, you risk introducing skew
between the two phases of the clock.
Currently the only known problem with PPR in this
context is that, as of 11/6/95, PPR 5.2.0 does not
understand that a single clock line can drive
EITHER:
1. INLATs with INVERTED G pins and OUTFF(T)/INFFs with
NON-INVERTED C pins
**OR**
2. INLATs with NON-INVERTED G pins and OUTFF(T)/INFFs
with INVERTED C pins
Solution 1:
Solutions 261 and 958 document how you can implement
dual phase clocks in an XC3000 device (APR won't do it for
you automatically). To retrieve these two documents via
the XDOCs email server, send email to xdocs@xilinx.com and
include the string "SEND 261 958" in the Subject field.
End of Record #945
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