Answers Database

What is needed to target 4000E speed grade 4000 designs using Verilog, Foundry and Synopsys


Record #985

Product Family:  Hardware

Product Line:  4000E

Problem Title:
What is needed to target 4000E speed grade 4000 designs using Verilog,
Foundry and Synopsys



Problem Description:
What is needed to target 4000E speed grade 4000 designs using Verilog,
Foundry and Synopsys

Foundry 7.x does not support 4000E devices per se, but there are -2 and
-3 speed files available that will allow you to implement 4000 functionality in

4000E parts to take advantage of the speed.  This solution record documents
th products you would need to do 4000 designs using Verilog for design entry, Sy
nopsys
for synthesis, Foundry for implementation, and Verilog-XL for simulation


Solution 1:

To implement designs 4000E speed grade designs, you need:

- Synopsys FPGA Compiler
- DS-SY-ADV, which includes Xilinx Synopsys Interface (DS401), XACT Core
   Tools, Foundry, and ES-Verilog.
- ES-Verilog beta libraries and interface for 4KE and 5K families, or
   DS-VIK,  the Foundry Verilog integration kit.  (The ES-Verilog beta
   interface and libraries are available via ftp (esv4ke5k.t.Z.uu), whereas
   DS-VIK is an additional cost item.)

Foundry supports translation of the synthesized EDIF output from
the Synopsys EDIF writer, but since Synopsys FPGA Compiler will often infer
XBLOX components for 4K devices, you will also need XSI and the XACT Core
Tools to support XBLOX.  The .xtf out of the Core Tools is  input to the
Foundry tools, and the resulting ncd file can either be translated to an LCA
using XLATE and processed by ES-Verilog, or fed directly to the DS-VIK kit
to generate a Verilog netlist.







End of Record #985