Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


XC3000: Place Block syntax for APR is different than for PPR, results inAPR Error 213.


Record #1033

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
XC3000: Place Block syntax for APR is different than for PPR, results
inAPR Error 213.



Problem Description:
Keywords: CLB, PPR, APR, XC3000, place block


Urgency: Standard

Description

The APR (for xc2000 and non "A" xc3000 devices) syntax for
a Constraint (.cst) file for place block is not the same
as the PPR (3000A) syntax for place block.  If the PPR
syntax is used for APR, the following error will be generated.

APR: In 'Place block' statement at line 1 of file design.cst --
APR: ERROR 213: Missing location name.


Solution 1:

The place block constraint file syntax for APR is:
PLACE BLOCK signal_name location;

For example to constrain an IO called input to pin 12
you would have:
PLACE BLOCK input P12;

The place block constraint file syntax for PPR (3000A devices) is:
PLACE BLOCK signal_name : location;
For example to constrain an IO called input to pin 12 the
syntax is:
PLACE BLOCK input : P12;



End of Record #1033

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents