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XABEL-CPLD, 9500: Controlling Global Net Utilization for 9500 designs with XABEL-CPLD


Record #1036

Product Family:  Software

Product Line:  Data I/O

Problem Title:
XABEL-CPLD, 9500:  Controlling Global Net Utilization for 9500 designs
with XABEL-CPLD



Problem Description:
This file contains information on controlling global
optimization.  This topic is concerned with controlling global net
utilization in XABEL-CPLD, and how to  influence a design to use
global nets in an XC9500 CPLD.


Solution 1:

In M1 (EDIF flow), to force an input to be mapped to a global clock (GCK), OE (G
TS) or set/reset (GSR) device pin, use:

  XILINX PROPERTY 'BUFG=CLK|OE|SR input_pin...';

(XEPLD PROPERTY syntax is obsolete in M1.)



Solution 2:


module opttest

TITLE 'Controlling Global Optimization'

"inputs
in1, in2, reset, clk, outen pin;

"outputs
 out1, out2 pin istype 'reg';

 equations

 out1.clk = clk;      " defining clock input
 out2.clk = clk;      " defining clock input
 out1 := in1;	      " defining equation
 out2 := in2;	      " defining equation
 out1.ar = reset;     " defining asynchronous reset
 out2.ap = !reset;    " defining asynchronous set
 out1.oe = outen;     " output enable
 out2.oe = outen;     " output enable

END		     " all modules require an END


This code shows two registered equations, 'out1', and 'out2'.
The input 'clk' is used as a direct clock input to 'out1' and
'out2'.  In addition, 'out1' and 'out2' are asynchronous reset
and set flip flops, respectively, with global output enable.



Global Set/Reset (GSR) net optimization:

  Figure one shows 'out1', and 'out2', using signal 'reset' of
 different polarities for asynchronous reset and set functions.
 The fitter software for XABEL-CPLD V6.0 will not use the GSR
 net for 'reset' because the XC9500 family of CPLD's has only
 one GSR net.  One net cannot have two different polarities.

If Figure 1 was changed to:

		    out1.ar = reset;
		    out2.ap = reset;

the fitter software would map 'reset' to the global GSR net.
Also, if more than one signal is used in the equation for
'out2.ap', the software would not map the asynchronous preset
 to the GSR net.  For example:

		    out2.ap = reset & in1;

The equation 'reset & in1' in the above case would be mapped to
a product term (p-term) equation.



Global Clock Net (GCK) net optimization:

  The fitter software for XABEL-CPLD V6.0 will map the 'clk'
input for Figure 1 to the global clock net, GCK1, in an XC9500
CPLD.  Changing the 'out1.clk' equation to:

		    out1.clk = clk & in1;

will cause the software to map 'clk' into a p-term clock
equation for both registers.  The reason the software does this
is to avoid additional skew between the input 'clk', and the
p-term clock equation, 'clk & in1'.  However, adding the
property statement:

		    XEPLD PROPERTY 'FASTCLOCK clk';

before the 'equation' key word causes the software to map the
signal 'clk' to the GCK net.

  If the equations for 'out1', and 'out2' were:

		    out1.clk = clk;
		    out2.clk = !clk;

no XEPLD PROPERTY statement would be required, since both
polarities of 'clk' can be mapped onto global clock nets.  For
instance, 'clk' would be mapped to one global net, and the
complement of 'clk' would be mapped to a second global net.



Global output enable (GTS) utilization:

  The code in Figure 1 will use the GTS net for 'outen' in an
 XC9500 CPLD.  If 'out2' was changed to:

		    out2.oe = !outen;

the software would map the complement of 'outen' to the global
net GTS2 in an XC9500 CPLD, while 'outen' would be mapped to
GTS1.

  If we changed 'out2' to be:

		    out2.oe = !outen & in1;

the software would not map 'outen' or it's complement to the GTS
nets in an XC9500 CPLD.  As in the case above for global clock
optimization, the software does this to avoid skew between
common signals.



Driving global nets from on-chip generated signals.

  Global nets can only be driven from I/O pins, not macrocell
feedback.  If you want to use an on-chip generated signal to
drive a global net, you must use pin feedback.	For example, in
the equation below, 'out1' uses the macrocell feedback of 'out2'
for it's output enable product term.

		    out1.oe = out2;

If the equation were changed to use pin feedback, as below,

		    out1.oe = out2.pin;

the fitter would map 'out2' to the global GTS net.

  The information above is given as a reference of how the
fitter software for XABEL-CPLD V6.0 performs global
optimization. The information does not illustrate all
possibilities to influence a design to use global optimization.














End of Record #1036