Answers Database

CONCEPT, COMPOSER, VERILOG (pre-M1 only): XC4000 ILD latch primitives are renamed in the pre-M1 Unified libraries


Record #1091

Product Family:  Software

Product Line:  Cadence

Problem Title:
CONCEPT, COMPOSER, VERILOG (pre-M1 only):  XC4000 ILD latch primitives
are renamed in the pre-M1 Unified libraries



Problem Description:
Keywords: XC4000 ild ild_1 ildi_1 ildx_1 ildxi_1 ildi1 ild1
ildx1 ildxi1 latch

Urgency: standard

General Description:
XC4000E Unified library latch Primitives which have
Underscore one's ("_1"s) in their names are renamed in
Concept, Composer, and Verilog by removing the
"_1" part of the name.

Version:  9404 through 9604 versions (pre-M1) of Concept,
Composer and Verilog libraries.




Solution 1:

The reason for doing this is because there is a potential for
naming conflicts when Cadence users run Vloglink to generate
a functional simulation netlist.  Vloglink by default takes
the SIZE property attached to a library component, and
attaches an "_SIZE" suffix to the name of the component.
This can cause a name collision if the underlying primitive
has a name with an "_1" extension, and the upper level macro
has a default SIZE value of 1.

For example, consider the case of an ILD macro, which is
built from an ILD_1 primitive.	If the SIZE property on the
macro is 1 (this is the default) Vloglink will add an "_1"
extension to "ILD", renaming it to ILD_1, and this will
cause a name conflict with the underlying "ILD_1".

Note that this is mainly an issue when:

  1. the Unified library specification specifies a *primitive*
     name having an "_1" suffix (macros do not have this
     problem);

  2. the user is using Vloglink to generate a functional
     simulation netlist.


The following primitive components are renamed:


Xilinx primitive       Concept/Composer
name in Libraries      /Verilog library
Guide		       component
-----------------      ----------------

ild_1			 ild1
ildi_1			 ildi1
ildx_1			 ildx1
ildxi_1 		 ildxi1




End of Record #1091