Answers Database

MAKEBITS TIE--Should all designs be tied?


Record #1104

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
MAKEBITS TIE--Should all designs be tied?


Problem Description:
Keywords: makebits tie recommendation

Urgency: standard

General Description:
The question often comes up as to what Xilinx's official
position is as far as the tying of designs.  Some
considerations are listed below.


Solution 1:

The main reasons for tying a design are to reduce power
consumption caused by floating internal nets, and to
reduce sensitivity of the programmed device to noise.
The MakeBits tie option defines all unused CLB and IOB inputs
and
consumes all available interconnect.  This guarantees that all unused
resources are at a known, non-floating logic level.

Tying a design is generally recommended for production designs.  In
contrast, it is not critical to tie a design during the debugging stage
of the design process unless it is a power-critical application.  Skipping the
tie operation during debug saves processing time.

The general rule is:  tie production designs whenever possible to reduce power
consumption and internal noise.

It should be noted that it may not always be possible to tie down a
design due to a lack of resources or routing congestion. From a
functionality standpoint, tying the design may also not be desirable if the
delay associated with tying unused interconnect to certain signals
slows them down to unacceptable levels.  The solution in such cases is to
tell Makebits to avoid using certain nets for Tie by marking them as Critical
before the Makebits -t is run.

Note also that tie remains an all-or-nothing process--that is,
if it is not possible to tie off *all* unused interconnect, *none* of
the unused interconnect gets tied.  This applies to all versions of
Makebits up to v5.2.1.






End of Record #1104