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BOUNDARY SCAN/JTAG: What is the bit order of the Instruction Register inXilinx FPGA's


Record #1172

Problem Title:
BOUNDARY SCAN/JTAG: What is the bit order of the Instruction Register
inXilinx FPGA's



Problem Description:
Keywords: instruction register, ir, length, order

Urgency: Standard

General Description:

What is the BIT-order and length of the Boundary Scan Instruction
Register in the Xilinx XC4000 and XC5200 families.



Solution 1:

The instruction register is 3 bits wide and the bit order is
I2-I1-I0. I0 is shifted out of TDO first, then I1, and then I2.



End of Record #1172