Answers Database

PCI macro: Fplan - Potential errors found in LOCs or constraints.


Record #1230

Product Family:  Software

Product Line:  Logicore

Problem Title:
PCI macro: Fplan - Potential errors found in LOCs or constraints.


Problem Description:
If you use the Floorplanner to floorplan the user portion of
your design with the PCI core provided, the following pop up
message about potential errors will be displayed when the design
is read into Floorplanner:

Potential errors found in LOCs or constraints.

Please see fplan.log for detailed description.

The fplan.log file will show the following warnings:

*** FPLAN: WARNING 12936:

Cannot place symbol $FG_PCI_LC_I/PCI-CSR/STATREG/Q14/
D on block CLB_R2C6.G because it is already occupied.

*** FPLAN: WARNING 12936:

Cannot place symbol $FG_PCI_LC_I/PCI-CSR/STATREG/Q12/
D on block CLB_R3C6.G because it is already occupied.

*** FPLAN: WARNING 12942:

The IOB named ADIO14 was not found in the design.

*** FPLAN: WARNING 12942:

The IOB named ADIO16 was not found in the design.

*** FPLAN: WARNING 12942:

The IOB named TESTBNCH/ADDR_OUT8 was not found in the
design.

*** FPLAN: WARNING 12942:

The IOB named TESTBNCH/ADDR_OUT17 was not found in the
design.

*** FPLAN: WARNING 12942:

The IOB named TESTBNCH/ADDR_OUT22 was not found in the
design.

*** FPLAN: WARNING 12942:

The IOB named TESTBNCH/ADDR_OUT23 was not found in the
design.


Solution 1:

The first two warnings occur because there are lower level
macros in the statreg schematic, called FSRE, that contain
FMAPs with an RLOCs=R0C0, but do not specific a .G or .F
extension. PPR will correctly place logic in both the F
and G function generator without needing the .F or .G extension;
however, the floorplanner incorrectly issues a warning on this
ambiguity which can be ignored. The other warnings about names
of certain IOBs not being found in the design originate from
those IOBs being used for feed-thrus. These warnings can also
be ignored.



End of Record #1230