Answers Database

PCI macro: Use of XSIMMAKE in timing simulation


Record #1232

Product Family:  Software

Product Line:  Logicore

Problem Title:
PCI macro: Use of XSIMMAKE in timing simulation


Problem Description:
Due to overly conservative I/O modeling, XSIMMAKE should not be
used to create the back-annotated simulation file. The following
steps create the correct set of files.


Solution 1:

1. Process the .lca file with lca2xnf using the -g option to
create an .xnf file.

	lca2xnf -g my_design.lca my_design.xnf

It is important that the .lca file has embedded timing
information, which is generated during the XMake process by
default. Alternatively, you may use the following command
prior to running the lca2xnf command:

	xdelay -d -w my_design.lca

This command adds the timing data and back-annotates it onto
the .lca file.

2. Run the model_io Perl script, (model_io version 2.01 or
higher should be used).  (The Perl script is located on PCI
CD-ROM)

This corrects known conservative modeling values for the setup/
hold and clock-to-output timing of the I/O flip-flops. The Perl
script provides the guaranteed data book values in the final
.xnf file (see the XC4000E Technical Data data sheet).

The Perl program version 5.00 or higher is required to execute
the model_io script.

For UNIX:

	perl perl/model_io my_design.xnf model_io.xnf

For DOS:

	perl perl\model_io my_design.xnf model_io.xnf

3. Run xnfba. This updates the .xnf file generated by model_io
with timing information.

	xnfba my_design.xff model_io.xnf -o my_design_time.xnf

4. Generate the required design wire files using xnf2wir. The
output filename from this process must match your top-level
design name. The resulting wire files contain the fully
back-annotated timing information. This is required by VIEWsim
to create the timing model.

For UNIX:

	xnf2wir my_design_time wir/my_design_time

For DOS:

	xnf2wir my_design_time wir\my_design_time

5. Create the timing simulation model.

	vsm my_design_time

6. Invoke the VIEWsim simulator.

	viewsim my_design_time

7. Execute the PCI test vector command file.

	sim testbnch.cmd



End of Record #1232