Answers Database

CADENCE, VERILOG-XL, X-BLOX: Error! Port (o) not found in module definition


Record #1250

Product Family:  Software

Product Line:  Cadence

Problem Title:
CADENCE, VERILOG-XL, X-BLOX:   Error! Port (o) not found in module
definition



Problem Description:
Keywords: cadence xblox x-blox verilog ifd ild ild

Urgency:  standard

General Description:
This error may arise in functional simuation if a design contains XBLOX
components, AND also has an input pad configuration that uses both the
registered and direct versions of the input signal, e.g:

					  O
PAD----x----------->IBUF---------------------->  **** logic *****
       |				  Q
       |___________--------___________________>  *** more logic ***
		   | D	Q |
		   |	  |
		   |clk   | IFD
		   |______|

the user may see the following message from Verilog-XL:

Error!	  Port (o) not found in module definition	    [Verilog-PNFMD]
	  "calcf.v", 25: .o(OUT1X[1])


The reason this occurs is because XNFPREP
is run on designs containing XBLOX when the funcnet(x) script is invoked,
and XNFPREP "merges" the parallel IBUF and IFD/ILD into an "INREG" if the
register is an IFD, and an "INLAT" having an "o" pin.

In both the INREG and the INLAT, the O pin represents the direct version
of the input signal (as opposed to the "q" pin, which represents the
registered version of the same signal).  The error is issued because there is
no support for an "INREG"/"INLAT" and the associated "O"  pin in the Verilog
simulation model library.




Solution 1:

The solution is to run Timenet on the design on an unrouted
netlist. The following explains how to run this script
without having to complete a place-and-route.

	1) Netlist your design
	2) cd to Xilinx run directory (default is /xilinx.run)
	3) xmake -G <design_name>
	4) Edit the <design_name.mak> file
	5) add route=false and placer_effort=1 options to the
	   ppr line.
	6) xmake <design_name.mak>  **NOTE the MAK extension**
	7) cd ../
	8) timenet <desig_name> 4000 -lwbverilog -r
	   <xilinx_run_dir> -x
	9) Invoke Verilog-XL with the +delay_mode_unit option to run
	   Verilog-XL in unit delay simulation mode.




End of Record #1250