Answers Database

4000E/5200 VERILOG Libraries are included on XACT v5.2.1 Core Tools CD and ftp site


Record #1271

Product Family:  Software

Product Line:  Cadence

Problem Title:
4000E/5200 VERILOG Libraries are included on XACT v5.2.1 Core Tools CD
and ftp site



Problem Description:
The 4000E and 5200 Verilog BETA Interface and libraries are included with
the 2000, 3000, 4000, and 7000 libraries on the XACTstep v5.2.1 CD.  They
may also be downloaded from ftp.xilinx.com, along with full documentation
in postscript format.

The Verilog-XL patch v2.2.8 for Sun4 that was required for proper simulation
of 4000E dual port and synchronous RAM platforms is available as a
two-part archive described below.  To properly simulate 4000E designs
containing dual port or synchronous RAM, you must either use this patch,
or the 2.3.3 version of Verilog-XL from the 9504 Cadence release.  You must
also invoke Verilog-XL with the +neg_tchk and +splitsuh options to allow
negative timing values and split setup and hold checks..

 NOTE:	No patch is required for the HP7 version of Verilog-XL.




Solution 1:

The ES-Verilog interface exists in archive form on the CD under
the xbbs/swhlp directory.

xil_vlog_intfc.sun4.tar.Z.uu  (Sun4)
xil_vlog_intfc.hp7.tar.Z.uu   (HP7)

The interface is not installed by the graphical workstation install.

They are also accessible from

    ftp://ftp.xilinx.com/pub/swhelp/cadence


    In this case the files are named:

		xil_vlog_intfc.sun4.tar.Z  (Sun4)
		xil_vlog_intfc.hp7.tar.Z   (HP7)

These archives are identical to the archives found on the XACTstep
Core Tools v5.2.1 CD-ROM.

Each archive includes the full documentation in postscript format:

	vlogintdoc.ps


To extract the ES-Verilog archive, navigate to the base directory for your
existing XACT or Cadence installation, copy the archive to this
location, and type the following:

	- uudecode <filename>.tar.Z.uu	 (skip this step for .Z files)
	- uncompress  <filename>.tar.Z.uu
	- tar xvf <filename>.tar


NOTES on simulating XC4000E designs with dual port or synchronous RAM:
---------------------------------------------------------------------

Proper simulation of 4000E designs with dual port or synchronous RAM
requires that:

1. If you are running Verilog-XL on the Sun4 platform, you must use
the proper version of Verilog-XL.  Either the Verilog-XL patch v2.2.8,
or Verilog-XL v2.3.3 from the 9504 Cadence release is required because
of a core dump problem with version 2.2.1 when the +neg_tchk option is
specified.  If the 9504 release is not available to you, download
the following archives for the v2.2.8 patch:


	vconfig03.23-p007sun4.t.Z.uu
	verilogxl02.20-s018sun4.t.Z.uu

The 2.2.1 version of Verilog-XL on the HP7 platform does not exhibit this
core dump problem.

2. When simulating a 4000E design with synchronous and/or dual port RAM,
you must invoke Verilog-XL with the +neg_tchk and +splitsuh options so that
Verilog-XL will accept the negative delay values used to model the RAM
behavior.


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Please contact Xilinx Technical Support at 1-800-255-7778 if you have
any problems accessing this archive.






End of Record #1271