Answers Database

PCI Macro: Why is the clock signal on the output of a BUF, not a BUFG?


Record #1285

Product Family:  Software

Product Line:  Logicore

Problem Title:
PCI Macro: Why is the clock signal on the output of a BUF, not a BUFG?


Problem Description:
In the PCI Macro schematic, the clock, called PCI_CLK, is the output of a
BUF.  This BUF is driven by a BUFGP.  The schematic appears like this:

	     clk    pci_clk
     |>---|>-----|>---------
   IPAD  BUFGP	 BUF   x

There is an X flag on the output net of the BUF.  Does this mean that the
clock signal is really the output of a regular buffer, and not a global
buffer?


Solution 1:

The clock signal, PCI_CLK, will be on a global net.

Since the X flag is only on the output net of the BUF, the
BUF will still get trimmed out, and collapsed into the BUFGP.
The X flag just serves to retain the name of the clock signal,
PCI_CLK.

So, after XNFPREP runs, the resulting netlist will have just
the BUFGP, whose output signal is called PCI_CLK.

The 'X' attribute on PCI_CLK is there to maintain naming.
Without maintaining the name, the guide file would fail.



End of Record #1285