Answers Database

Synopsys : How to use OSC5, OSC52, and CK_DIV Cells from the XC5200 Synthesys Libraries


Record #1289

Problem Title:
Synopsys : How to use OSC5, OSC52, and CK_DIV Cells from the XC5200
Synthesys Libraries



Problem Description:
Xilinx does not recommend using the OSC5, OSC52, and CK_DIV cells in the XC5200
synthesis libraries.  Due to a limitation in most synthesis tools, you cannot at
tach parameters or attributes to synthesized or instantiated cells.  The OSC5, O
SC52, and CK_DIV cells require the DIVIDE1_BY or the DIVIDE2_BY attribute to spe
cify appropriate clock division ratios.  Currently, the FPGA Compiler and the De
sign Compiler write netlists that include these cells without the required attri
butes.	This causes XNFPREP to generate XNFPREP error 4714.  However, you can us
e the OSC5 or CK_DIV module by modifying and instantiating the .xnf files.


Solution 1:

How to use OSC5 and CK_DIV with Synopsys :

1.  Go to the DS401_install_directory/data/synopsys/xprim_5200 directory.

2.  Copy the CK_DIV.XNF or OSC5.XNF file to your working directory.

3.  Add the DIVIDE1_BY or DIVIDE2_BY attributes to the XNF file, as shown below.
  You must use the DIVIDE1_BY attribute with the OSC1 output and the DIVIDE2_BY
attribute with the OSC2 output.  When the design is implemented, these XNF files
 are merged in and the DIVIDE1_BY anf DIVIDE2_BY attributes are preserved.


The following is the origional OSC5.XNF file :

LCANET, 6
SYM, $1I1, OSC52, SCHNM=OSC5, LIBVER=2.0.0
     PIN, OSC1, O, OSC1
     PIN, OSC2, O, OSC2
END
EOF

Add attributes to the file as shown.  Refer to the Liraries Supplement Guide for
 the appropriate valus of X and Y.

LCANET, 6
SYM, $1I1, OSC52, SCHNM=OSC5, LIBVER=2.0.0, DIVIDE1_BY=X, DIVIDE2_BY=Y
     PIN OSC1, O, OSC1
     PIN OSC2, O, OSC2
END
EOF


The following is the origional CK_DIV.XNF file :

LCANET, 6
SYM, $1I1, OSC52, SCHNM=CK_DIV, LIBVER=2.0.0
     PIN, C, I, C
     PIN, OSC1, O, OSC1
     PIN, OSC2, O, OSC2
END
EOF

Add the Attributes to the file as shown.  Refer to the Libraries Supplement Guid
e for the appropriate values of X and Y.

LCANET, 6
SYM, $1I1, OSC52, SCHNM=CK_DIV, LIBVER=2.0.0, DIVIDE1_BY=X, DIVIDE2_BY=Y
     PIN, C, I, C
     PIN, OSC1, O, OSC1
     PIN, OSC2, O, OSC2
END
EOF


4.  Instantiate the OSC5 or CK_DIV module in your design.



Solution 2:

How to use the OSC5 and CK_DIV with Synopsys in A1.4


1. Instantiate the OSC5 or CK_DIV in your HDL code.

2. Add the DIVIDE1_BY or DIVIDE2_BY attributes to the SXNF file, as shown below.
  You must use the DIVIDE1_BY attribute with the OSC1 output and the DIVIDE2_BY
attribute with the OSC2 output.  The OSC5 and CK_DIV will be written into
the SXNF file from FPGA Compiler.:

Original SXNF file with OSC5

LCANET,5
PROG,Synopsys,1997.08,"Created from test.db"
PART,5202PC44-3
SYM,MYCLOCK,OSC5
PIN,OSC1,O,clock,,
END
.
.
.
.


Modified SXNF file:

LCANET,5
PROG,Synopsys,1997.08,"Created from test.db"
PART,5202PC44-3
SYM,MYCLOCK,OSC5,DIVIDE1_BY=4,DIVIDE2_BY=2
PIN,OSC1,O,clock,,
END
.
.
.



Original SXNF file with CK_DIV

LCANET,5
PROG,Synopsys,1997.08,"Created from test.db"
PART,5202PC44-3
SYM,MYCLOCK,CK_DIV
PIN,OSC1,O,clock,,
END
.
.
.
.


Modified SXNF file:

LCANET,5
PROG,Synopsys,1997.08,"Created from test.db"
PART,5202PC44-3
SYM,MYCLOCK,CK_DIV,DIVIDE1_BY=4,DIVIDE2_BY=2
PIN,OSC1,O,clock,,
END
.
.
.

(3) Place and route the design using A1.4



End of Record #1289