Answers Database

M1.3/M1.4 CONCEPT2XIL/HDLCONFIG/VAN/SIR2EDIF: "Architecture not found" errors


Record #1302

Product Family:  Software

Product Line:  Cadence

Problem Title:
M1.3/M1.4 CONCEPT2XIL/HDLCONFIG/VAN/SIR2EDIF: "Architecture not found"
errors



Problem Description:
Keywords:  concept concept2xil architecture hdlconfig van sir2edf logiblox pre-M
1.0 VAN cds.lib

Urgency:  standard

General Description:

CONCEPT2XIL calls three subprograms: HDLCONFIG, VAN (Verilog
Analyzer), and SIR2EDF.  The general meaning of "architecture
not found errors" is that one of these programs could not find
a certain model, or "view" of a given cell in your design.
This cell could either be one of the subblocks
in your design, or a library component instantiated in your
design.


SAMPLE ERROR MESSAGE:

<output>
   Occurrence p1$9p -> calc_lib.synonym.hdl:
   Error! Architecture not found in your design library
</output>

The occurrence name (p1$9p) corresponds to the value of the
PATH property in your Concept schematic. The expansion of the
cell name, in terms of the analyzed Verilog, is
<library>.<cell>.<view>.  The netlister first looks for the
cell and view in the Unified Library.  If it doesn't find
them there, it will look in your design library.  In the
example above, the HDL view of a cell called a "synonym" body
could not be found in the calc_lib library for the design
called "calc".


"architecture"

- refers to a "block" or component in your design (the
reference to "architecture"  originated from the keyword, "ARCHITECTURE" in the
VHDL language, which just means
"design block").

"view"

- one of the representations or models of that
"architecture" or block.


For Concept designs, you can have any of the following views
(or models) for a given cell:

 - a Schematic view,
 - a LOGIC view
 - an HDL view
 - a Symbol (Body) view.


The LOGIC view is generated by HDL Direct when you save your
Concept schematic, and consists of:

 - viewprps.prp properties file (contains all schematic
   properties)

 - a verilog.v file (structural Verilog description of the
   design block)

 - a (S)tructural (I)ntermediate (R)epresentation format
   file, which is generated by the VAN Verilog Analyzer. A
   SIR file is part of the HDL view of a block.

The SIR file is generated by VAN (Verilog Analyzer), one of
the subprograms called by the CONCEPT2XIL script.


In general, when you get an "ARCHITECTURE NOT FOUND" error,
this indicates that a particular view is absent, either:

 - in one of the cells in the TARGET LIBRARY defined in your
   CDS.LIB file(for example, xce4000ex_syn), or

 - in one of your user blocks in the DESIGN_LIB directory
   that CONCEPT2XIL creates for your design.

The exact "view" that is missing depends on which CONCEPT2XIL
subprogram (VAN (Verilog Analyzer), or SIR2EDF) issues the
error message.



Solution 1:

If the error comes from the SIR2EDF subprogram, this means
that the SIR2EDF subprogram has searched through both the
target and design libraries:

	<target_arch>_syn
	<design>_lib

and was unable to find a .SIR file in the HDL view
(subdirectory) for a particular design block or subblock.

   For a given library cell (usually in

	     $XILINX/cadence/data/target_library_syn)

   or user block, (in <design>_lib in your run directory) you
   should see an "hdl/" subdirectory underlying it that looks
   something like this:

    	      hdl/   verilog_lib/

   If the library cell or user block has been successfully
   processed by VAN, there should be a .SIR file in the HDL/
   subdirectory or "view:

     master.tag    verilog.v@	 vlog004u.sir  vlog004u.vla
				 ^^^^^^^^^^^^

Note the .sir file, vlog004u.sir in this example.

If the error is issued on some USER BLOCK in the design, check that:

 - the CDS.LIB file exists,

 - a .SIR file exists in the "hdl/" view for the given
   block in your <design>_lib directory.



If the error is issued on a primitive XILINX LIBRARY
component, check:

 - that the CDS.LIB file exists and
 - the path to the target library specified in it is correct,
 - the specified cell exists in this library,
 - the cell in the library you are targeting has an "hdl"
   view (subdirectory) containing a .SIR file.
   (If the .SIR is missing, it may be that the library was
   not VAN-analyzed successfully, or that the library was
   somehow corrupted.)
 - the .SIR file in the hdl subdirectory of the library cell
   is the same version as those written to

	<rundir>/<design_lib>/<cell>/hdl.


Example:

> Running sir2edf version 97A-2.4 11/05/96 10:16 (cds9252).
> Copyright (c) 1992-1995 Cadence Design Systems. All Rights Reserved.
>
> Initializing environment ...
> Loading property format file ...
> Loading design unit ...
> Expanding design hierarchy ...

> Occurrence p1$9p -> calc_lib.synonym.hdl:
> Error! Architecture not found in your design library
>

In this case the error is reported on a component called
"synonym" in a design called "calc".  This indicates there is
a component containing a SYNONYM body or cell.

The reason an error is issued is because CONCEPT2XIL requires
that only HDL Direct compliant library components be used,
and "SYNONYM" happens to be a non-HDL Direct component from
the STANDARD library.  Components from the STANDARD library
are NOT HDL Direct compliant.

The solution is to either :

1. add a library to the CDS.LIB that contains an HDL Direct
   compliant SYNONYM cell, or
2. remove the offending cell from the design and substitute a
   different component that *is* HDL Direct compliant.


If, on the other hand, the library cell is a MACRO, the
<design>_lib design library should have a cell corresponding
to this macro, and that cell should have an HDL view
containing a .SIR file for the macro.

If the cell for the library macro is missing in the
<design>_lib library, this may be because of some other
error in the schematic that was not corrected.	Open
the schematic in Concept, save it, and look for schematic
errors that may have been ignored previously, like
errors about unlabeled nets connected to the cell in
question, or to other blocks in the design.









Solution 2:

If the error is coming from the VAN subprogram, check the
CDS.LIB file in your design directory and make sure that:

- the CDS.LIB file exists, and the target library
  "<target_arch>_syn" is defined in your cds.lib file.

- the path to the target library specified in the cds.lib
  file is correct.

- the referenced cell exists in the library you're targeting
  in your cds.lib.

  (Note that the name must match when it does a case-
  sensitive search.  If it does not, it may be that the
  library was not VAN-analyzed.)

- You have enabled HDL Direct in Concept before saving each
  block of your design.  This will generate the views
  required by CONCEPT2XIL for each block of your design.




Solution 3:

Another cause of this problem is trying to use pre-M1
libraries in your design (xblox5, xc4000, xm4000, etc.).

CONCEPT2XIL supports M1 Concept libraries only.



Solution 4:

<UL>If you have LOGIBLOX modules in your design</UL>:


This error may also be seen from the SIR2EDF subprogram of
CONCEPT2XIL if you are using LogiBLOX in your design.
Integrating the LogiBLOX module into your Concept
schematic requires that you use GENVIEW to generate a symbol
from the LogiBLOX-generated .v file.  GENVIEW copies the
LogiBLOX .v file into the logic view for that block as

       block_name/logic/verilog.v

There is an additional, required step that you must do
manually after the symbol body is generated--you must edit
the verilog.v file and add the following parameter
declaration to the beginning of the module declaration for
the LogiBLOX module:

       parameter cds_action="ignore";

This lets the CONCEPT2XIL netlister know that it should not
expect to find any more levels of hierarchy below this block,
otherwise you will get an error from SIR2EDF that looks like:

<output>
   Running sir2edf version EXP-2.9 01/12/97 20:17 (cds9244).
   Copyright (c) 1992-1995 Cadence Design Systems. All Rights
   Reserved.

   Initializing environment ...
   Loading property format file ...
   Loading design unit ...
   Initializing mapping tables ...
   Expanding design hierarchy ...
   Occurrence FLOP0 -> test_lib.X_FF.hdl:
   Error! Architecture not found in your design library
</output>

In the Alliance Pre-release (v1_2.11), there was also a bug
in LogiBLOX (Reference #15910) in which it would invoke
NGD2VER with the -ul option.  The effect of this was the
inclusion of a `uselib reference in the .V file pointing to
SIMPRIM Verilog library that may be cancelled out by other
`uselib directives elsewhere in the design.  This causes a
problem if there are both LogiBLOX and non-LogiBLOX
components in the design.  The net result is the same type of
error from SIR2EDF:

<output>
   Expanding design hierarchy ...
   Occurrence FLOP0 -> test_lib.X_FF.hdl:
   Error! Architecture not found in your design library
</output>

The exact component flagged will depend on what library
primitives the LogiBLOX module contains.  In this case the
module was a register, so an X_FF flip-flop is flagged first.



Solution 5:

This error is also seen in SIR2EDF if there is a "use"
directive in the global.cmd, but there is a missing reference
to a user-defined subblock in the .WRK file (SCALD user
library mapping file) for the project directory.



End of Record #1302