Answers Database

VERILOG-XL: Unconnected CE pin on register causes output to go unknown ("X")


Record #1337

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG-XL:  Unconnected CE pin on register causes output to go unknown
("X")



Problem Description:
There was a bug in the Xilinx Verilog-XL Unified libraries prior to
the XACT 5.2.1 release in which flipflop outputs would go to X if
CE was not tied to a known state in the design.


Solution 1:

The problem was a bug in the libraries across all families, and
has been fixed in v5.2.1 of the ES-Verilog archive.  The fix was
to define the CE pin as "tri1" so that it would float to logic level 1
when unconnected.

This archive is available on the XACTStep v5.2.1 CD-ROM.  See Solution 1107
for instructions on installing this archive.



End of Record #1337