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XNF2VERILOG/XNF2CDS may produce a net name that overlaps or conflicts with the name of another design element


Record #1339

Product Family:  Software

Product Line:  Cadence

Problem Title:
XNF2VERILOG/XNF2CDS may produce a net name that overlaps or conflicts
with the name of another design element



Problem Description:
Keywords:  Verilog xnf2verilog xnf2cds name overlap same
conflict

Urgency: standard

General Description:
There is a potential for name conflicts or overlaps
occurring in Verilog netlists generated by XNF2CDS or
XNF2VERILOG if the following conditions are true:

1. The names you select contain underscores;

2. Net or block names in the input XNF file use "/" symbols
as hierarchy separators;

3. Your design is hierarchical, and the root of some of the
net names you assign are the same as the name of some
hierarchical block in your design.

Naming overlaps can arise under these conditions
because XNF2CDS and XNF2VERILOG converts forward slash ("/")
hierarchy separation symbols to underscore symbols ("_").
Both programs convert the "/" because "/"'s are not legal
characters in Verilog identifier strings.

For example, consider the case of a design containing a
bus at the top level called "DEMUX_DATAI".  Bit 0 of the
bus at the top level would be written out as "DEMUX_DATAI<0>"
in the XNF file:

	SYM, XSYM36, OBUF, LIBVER=2.0.0, FAST
	    PIN, GTS, I, STARTUPGTSBUFOUT,
	    PIN, O, O, DEMUX_DATAI<0>,
	    PIN, I, I, N1676, 7.0
	END

Now say the design also contains a hierarchical block at the
top level called "DEMUX", which has a bus called "DATAI" in
its underlying schematic.  Bit 0 of the DATAI bus in the
flattened XNF file would be written out as "DEMUX/DATAI<0>":

	SYM, DEMUX/DATAI<0>, DFF, LIBVER=2.0.0, INIT=R
	    PIN, Q, O, DEMUX/DATAI<0>, 2.8
	    PIN, D, I, DATAI_IN<6>1,
	    PIN, C, I, N1602, 1.8
	    PULSE, C, +, 4.0
	    PIN, GSR, I, STARTUPGSRINVOUT, 81.6
	    PULSE, GSR, +, 70.6
	    SETUP, D, C, +, 1.0, 2.0
	END

When XNF2CDS or XNF2VERILOG converts the flattened input XNF
to Verilog, it will convert the "/" to an underscore,
giving you the converted name of "DEMUX_DATAI<0>",
which now conflicts with the name of the bus bit at the
top level of the design.


	fdce NDEMUX_DATAI_6_ (.clr(XGND), .ce(XVDD),
	  .gsr(STARTUPGSRINVOUT), .c(N1602),
	  .d(DATAI_IN_6_1), .q(DEMUX_DATAI_0_));


	obuf XSYM36 (.i(N1676), .o(DEMUX_DATAI_06_),
	  .gts(STARTUPGTSBUFOUT));


Notice the signal name for the 'o' pin of the obuf is the
same as the signal name for the 'q' pin of the fdce.

XNF2CDS and XNF2VERILOG do not check to see if a signal
already exists when legalizing Verilog-illegal names in a
design.



Solution 1:

To resolve the conflict, be judicious in your choice of
names for top level nets and blocks, as well as the names of
your submodules, keeping in mind the conversions that
will occur in hierarchical names during the netlisting
process.

For example, if you have a subblock called DEMUX, avoid
naming any top level interface signals "DEMUX_xxxx".




End of Record #1339