Answers Database

Foundation XVHDL, JTAG: How to instantiate the BSCAN symbol for BoundaryScan


Record #1362

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL, JTAG: How to instantiate the BSCAN symbol for
BoundaryScan



Problem Description:
Keywords: xvhdl, foundation, bscan, jtag, vhdl, xc4000, xc5200

Urgency: Standard

General Description:
Examples on how to instantiate the BSCAN symbol in Foundation XVHDL,
both for the XC4K and XC5K families:

Make sure that you are using XVHDL(Metamor) v 2.4.0 or later
with these examples.  Version 2.4.4 of XVHDL is available on
the Xilinx FTP site:

ftp://ftp.xilinx.com/pub/swhelp/foundation/spxv.exe

*NOTE* This file is valid only for Foundation releases 6.x.


Solution 1:

-- XC5200 example of instantiating the BSCAN symbol

entity example is
	port (a, b: in bit; c: out bit);
end example;


architecture xilinx of example is

component bscan
  port(tdi, tms, tck: in bit; tdo: out bit);
end component;

component tck
  port ( i : out bit );
end component;

component tdi
  port ( i : out bit );
end component;

component tms
  port ( i : out bit );
end component;

component tdo
  port ( o : in  bit );
end component;

component ibuf
	port (i: in bit; o: out bit);
end component;

component obuf
	port(i: in bit; o: out bit);
end component;

signal tck_net, tck_net_in  : bit;
signal tdi_net, tdi_net_in  : bit;
signal tms_net, tms_net_in  : bit;
signal tdo_net, tdo_net_out  : bit;

begin


u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net_out);


u2: ibuf port map(i=>tck_net_in, o=>tck_net);
u3: ibuf port map(i=>tdi_net_in, o=>tdi_net);
u4: ibuf port map(i=>tms_net_in, o=>tms_net);

u5: obuf port map(i=>tdo_net_out, o=>tdo_net);

u6: tck port map (i=>tck_net_in);
u7: tdi port map (i=>tdi_net_in);
u8: tms port map (i=>tms_net_in);

u9: tdo port map (o=>tdo_net);

process(b)
begin
if(b'event and b='1') then
 c <= a;
end if;
end process;


end xilinx;







Solution 2:

-- XC4000/XC4000E example of instantiating the BSCAN symbol

entity example is
	port (a, b: in bit; c: out bit);
end example;


architecture xilinx of example is

component bscan
  port(tdi, tms, tck: in bit; tdo: out bit);
end component;

component tck
  port ( i : out bit );
end component;

component tdi
  port ( i : out bit );
end component;

component tms
  port ( i : out bit );
end component;

component tdo
  port ( o : in  bit );
end component;



signal tck_net	: bit;
signal tdi_net	: bit;
signal tms_net	: bit;
signal tdo_net	: bit;

begin


u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net);

u2: tck port map (i=>tck_net);
u3: tdi port map (i=>tdi_net);
u4: tms port map (i=>tms_net);
u5: tdo port map (o=>tdo_net);

process(b)
begin
if(b'event and b='1') then
 c <= a;
end if;
end process;


end xilinx;







End of Record #1362