Answers Database

PCI macro: Information on pipelining signals in PCI designs


Record #1369

Product Family:  Software

Product Line:  Logicore

Problem Title:
PCI macro: Information on pipelining signals in PCI designs


Problem Description:
In the PCI macro, an advanced design technique know as pipelining
is required. What is this, why is this required, and how is it
implemented?


Solution 1:

What is pipelining?

Pipelining signals in PCI designs requires introducing the signal up to two
clock cycles in advance. This is done by registering the signal to insure
that it will arrive desired location within the 30ns clock period. Please
reference figure 9 in the PCI User's guide.

Why do we need to pipeline signals?

This is required because PCI has strict timing requirements which can
only be met by a pipelined design, especially if the user is using
either burst, 33MHz, or an initiator in their design. Any of these items
can contribute to the difficulty of the design; using all of them can
make a design very difficult to meet timing.

How do I implement it?

Below is a design without pipelining, which will require users to present
data on the input ONE clock cycle ahead. This path doesn't require
pipelining if the total path delay is < 30ns.

	 ---------	 -------------	     ----------
 Input	 | User  |	 | Logicore  |	     | IOB FF |
-------->| Comb. |------>|   PCI     |------>|	      |---> PCI BUS
	 | Logic |	 | Interface |	     |>       |
	 ---------	 -------------	     ----------
	Total path delay
|-----------------------------------------------------|
Total path delay = User Comb Logic + PCI Comb Logic + FF Setup.

However a lot of critical signals have either high fanout or many levels of
combinatorial delays in Logicore PCI interface, resulting is some signals
being very close to 30ns (33Mhz). Thus the 30ns specification will be
exceeded with only a few levels of User Combinatorial Logic.

Therefore a pipelined design will give designer a lot more flexibility in
designs, allowing more levels of User Combinatorial Logic since it
separates out the delay path into two pieces, path delay 1 and path delay 2.
The critical path is the longer path of the two and now you can have more
levels of logic for User Combinatorial logic. However, the data has to
be presented on input signal TWO clock cycles ahead of the time it needs
to be presented on the PCI bus.

	---------      ------	  -------------       ----------
 Input	| User	|      |    |	  | Logicore  |       | IOB FF |
------->| Comb. |----->|FFS |---->|   PCI     |------>|        |---> PCI BUS
	| Logic |      |>   |	  | Interface |       |>       |
	---------      ------	  -------------       ----------
	path delay 1			 path delay 2
|---------------------------|	  |-----------------------|

In the Xilinx PCI v1.1 User's Guide, the following list of signals are
timing critical in all LogiCore PCI designs and may require special attention
when connected to the user application.

IRDY-  - A heavily loaded signal that connects to the Target state machine.

TRDY-  - A heavily loaded signal that connects to the Initiator state machine.

ADDR_VLD - A heavily loaded signal, typically used in Target-side
applications. Connects to FRAME- internally to the LogiCore macro.

DATA_VLD - Becomes heavily loaded in most user applications. DATA_VLD is not
used within the LogiCore interface. However, DATA_VLD uses IRDY-, TRDY-,
S_DATA, and M_DATA as inputs, which are all timing critical signals
themselves. For Initiator applications, the critical path is most likely
from DATA_VLD through the COMPLETE logic.

READY - Connects to the Target and Initiator state machine control logic
through multiple layers of logic. Drive READY from a flip-flop, if possible.
The most timing critical path is from READY to the IRDY- and TRDY- outputs on
the PCI bus.

TERM - Connects to the Target state machine control logic through multiple
layers of logic. Drive TERM from a flip-flop, if possible. The most timing
critical path is from TERM to the TRDY- and STOP- outputs on the PCI bus.

KEEPOUT - Connects to the internal output-enables driving data onto the
internal ADIO[31:0] bus. The most timing critical path is from KEEPOUT,
through the output enable (OE_ADI) driving incoming data onto ADIO[31:0], to
any destination connected to the ADIO[31:0] bus.

S_DATA - Becomes heavily loaded in most user applications. The LogiCore
interface uses an internally duplicated copy of S_DATA.

Critical signals used in Target/Initiator Applications:

FRAME- - A heavily loaded signal used throughout the LogiCore interface and
the user application. In Target/Initiator applications, the FRAME- signal
becomes even more heavily loaded because it connects to the Initiator control
logic. Unfortunately, FRAME- cannot be internally duplicated due to PCI
loading restrictions.

COMPLETE - Is an input from the user application. It drives the IRDY- and
FRAME- logic in the Initiator state machine. The critical path is usually
from DATA_VLD, through COMPLETE, to setup on the FRAME- output on the PCI
bus. Floorplanning COMPLETE and its associated logic helps to reduce this
path.

M_ADDR- - Connects to the output-enables driving the Initiator's start address
onto the ADIO[31:0] internal bus. This path has little timing margin and may
require preplacement using the Floorplanner tool. Using the XDelay timing
analyzer, critical paths through M_ADDR- originate from the FRAME-, IRDY-, or
GNT- signals on the PCI bus.

M_DATA - Becomes heavily loaded in most user applications. The LogiCore
interface uses an internally duplicated copy of M_DATA.



End of Record #1369