Answers Database

Foundation XVHDL: How to lock down I/O pins


Record #1372

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL:  How to lock down I/O pins


Problem Description:
Keywords:  Metamor, I/O, pins, loc

Versions:  F6.x, F1.3/F1.4

Urgency:  Standard

General Description:

To lock down I/O signals to specific pins on the target
device, use the 'PINNUM' attribute in the VHDL code as shown
below.	Either declare the pinnum attribute in the entity, or
declare the Metamor library, in which the pinnum attribute is
declared.

Alternatively, pins may be constrained through a UCF file
(F1.x only), as described in (Xilinx Solution 1604).


Solution 1:

--Example of using the PINNUM attribute:

library IEEE;
use IEEE.std_logic_1164.all;

library METAMOR;
--Package attributes contains declarations of the Metamor
--specific synthesis attributes.
use METAMOR.attributes.all;

entity FLOP is
   port (CLK, DIN, RESET: in std_logic;
	INBUS: in std_logic_vector (3 downto 0);
	DOUT: out std_logic;
	OUTBUS: out std_logic_vector (3 downto 0));

   attribute pinnum of DIN: signal is "p20";
      -- lock DIN to p20
   attribute pinnum of INBUS: signal is "p16, p17, p18, p19";
      -- lock INBUS3 to p16 ... INBUS0 to p19.
end FLOP;

architecture LOCTEST of FLOP is
begin
   process (CLK, RESET)
   begin
      if RESET='1' then
	 DOUT <= '0';
      elsif (CLK'event and CLK='1') then
	 DOUT <= DIN;
      end if;
   end process;

   OUTBUS <= not INBUS;

end LOCTEST;



Solution 2:

In the case of PG/BG, Ceramic Pin Grid Array/Ball Grid Array
packages, the syntax is as follows:


  attribute pinnum of DIN: signal is "A20";
      -- lock DIN to Row A, Col. 20



End of Record #1372