Answers Database

Viewsynthesis: STARTUP instantiation


Record #1445

Product Family:  Software

Product Line:  ViewLogic

Problem Title:
Viewsynthesis: STARTUP instantiation


Problem Description:
STARTUP instantiation is not properly supported by either Viewsynthesis
v5.0.2x or Viewsynthesis v7.2. It is ignored and removed from the design.

The Startup block will be automatically inferred by Viewsynthesis 7.31 and newer
.


Solution 1:

The proper way to instantiate the STARTUP symbol in the
code should be the following:

library synth;
use synth.vhdlsynth.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tstartup is
	port(DATAIN : in std_logic_vector(4 downto 0);
		CLOCK, CLEAR : in std_logic;
		DATAOUT: out std_logic_vector(4 downto 0));
end tstartup;

architecture xilinx of tstartup  is

component STARTUP port (GSR: in std_logic);
		end component;

begin

U1 : STARTUP port map (gsr => CLEAR);

P1 : process (CLOCK, CLEAR)
begin
	if (CLEAR='1') then
	 DATAOUT <= "00000";
	 elsif(clock'event and CLOCK='1') then
		DATAOUT <= DATAIN;
	end if;
	end process;
end xilinx;


The problem is that ViewSynthesis deletes components that have
INPUTS ONLY.

The workaround is to instantiate the part outside of
ViewSynthesis, as in a netlist or schematic.




End of Record #1445