Answers Database

FGPA Express: How do you use pullups or pulldowns?


Record #1481

Product Family:  Software

Product Line:  Synopsys

Problem Title:
FGPA Express: How do you use pullups or pulldowns?


Problem Description:
Keywords: pullup, pulldown, instantiate, FPGA Express, Foundation Express

Urgency: Standard

General Description:
There are two ways to place pullups in your design.

1. Pullups or Pulldowns can be specifed after the user has 'implemented' the
design.

2. Pullups or Pulldowns can be instantiated in the HDL code.


Solution 1:

Pullups or Pulldowns for Ports Only can be specified in the Constraints GUI.

(1) After 'implementing' the design in FPGA Express, right-click on the
implemented design in the project window and select Edit Constraints.  This
will bring up the constraints window.

(2) The 'Ports' display will list all the external pins for a given design.
There is a column in this display called 'Resistance'.	Selecting the
'Resistance' column that corresponds to the pin you want, select the type of
resistance you would like: 'PULLUP' or 'PULLDOWN'.

(3) Close the Constraints window and optimize the implementation.



Solution 2:

Pullups or Pulldowns can be instantiated in the HDL code.  Pullups can be
instantiated for use with internal logic, and Pullups or Pulldowns can be
instantiated for external pins.

VHDL Example:

component PULLUP
     port (O : out STD_LOGIC);
end component;

...

U1: PULLUP port map (O => signal);



Verilog Example:

PULLUP U1 (.O(signal));




NOTES:

1. Pulldowns can only be used with external I/O.

2. Pullups can be used with external I/O, or with internal logic like tri-state
    (BUFT, BUFE) or open-drain (DECODE, WAND, WORAND) elements.  If pullups
    are instantiated in situations where they cannot be legally used, they
    will not be written into the XNF file by Express.

3. Pullups are not required (or allowed) in XC9500 designs.



Solution 3:


One fact that a designer needs to know is that you cannot directly drive an inpu
t port with a pullup. Therefore if you want to place a pullup on a input port yo
u must create a temporary signal that is driven by the input port. Then use the
temporary signal in the pullup port map.

A VHDL Example:

Placing a Pullup in A.

Entity test is
     port (A : in std_logic;
	   B : out std_logic);
end test;

Architecture RTL of Test is

component PULLUP
     port (O : out STD_LOGIC);
end component;

signal temp : std_logic;

begin

temp <= A;

U1: PULLUP port map (O => temp);



End of Record #1481