Answers Database

Foundation XVHDL: Using CLB Latches


Record #1486

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL:  Using CLB Latches


Problem Description:
Which Xilinx architectures support latches in the CLB, and
how should I write my VHDL code in order to properly use
latches?

For information on using Input Latches, please refer to
(Xilinx Solution 2962).


Solution 1:

XC3000 Family
-------------
XC3000 family devices do not have latches available in the
internal logic, but they do have input latches.

For information on using Input Latches, please refer to
(Xilinx Solution 2962).

Attempts at implementing internal latches should be avoided,
as the latch may be implemented with gates, and combinational
loops will result.  Combinational loops cause long synthesis
runtimes, and do not have reliable timing characteristics.
D flip-flops should be used instead.



Solution 2:

XC4000E Family
-------------
XC4000E devices, like the XC3000 family, do not have
latches available in the internal logic, so latches may be
implemented using gates.  However, unlike the XC3000, the
XC4000E also has the option to use RAM to implement latches
without combinatorial loops.  XVHDL can infer RAM if an
internal latch is described in the VHDL code.  (Note that this
feature is only supported in the Foundation XVHDL (Metamor)
compiler.  With Foundation Express, the latch will be created
out of combinatorial gates and feedback.)

See the resolution titled
"Example: Internal Latch" for example VHDL code.



Solution 3:

XC5200 Family
-------------
XC5200 family devices have latches available in the internal
logic, but no input latches (input latches are replaced with
an input buffer and an internal latch).  Latches may either
be inferred or instantiated with XC5200 designs.

See the resolution titled
"Example: Internal Latch" for example VHDL code.



Solution 4:

XC4000EX/XL
===========

The XC4000EX/XL families do contain latches in the CLBs.
Latches may be inferred by the XVHDL and Foundation Express
compilers.

See the resolutions titled
"Example: Internal Latch" for example VHDL code.




Solution 5:

Example: Internal Latch
-----------------------
-- This example VHDL code will infer a combinational feedback
-- loop in an XC3000 family device, and should not be used
-- for that architecture.
-- A RAM will be inferred in an XC4000E family device.
-- An internal latch will be inferred in an XC4000EX/XL device.
-- An internal latch will be inferred in an XC5200 device.

library IEEE;
use IEEE.std_logic_1164.all;

entity D_LATCH is
   port (GATE, A, B: in std_logic;
	 Q: out std_logic);
end D_LATCH;

architecture BEHAV of D_LATCH is
   signal DATA: std_logic;
begin
   DATA <= A and B;
   process (GATE, DATA)
   begin
      if (GATE ='1') then
	 Q <= DATA;
      end if;
   end process;
end BEHAV;





End of Record #1486