Answers Database

Foundation XVHDL: Using Timespecs


Record #1487

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL:  Using Timespecs


Problem Description:
Keywords:  timespec, tnm, ucf, cst, metamor

Versions:  F6.x, F1.3/F1.4

Urgency:  Standard

General Description:

The XACTStep and M1 Implementation software allows users to set timing requireme
nts on various
paths in the design.  By attaching TNM attributes to
instances in the design, and then setting point-to-point
timespecs, timing-critical paths can be controlled.  The
process for using timespecs with a Foundation VHDL design is
as follows:

1. Attach 'TNM' attributes to PADs, Flip-Flops, RAMs, Latches
   in the VHDL code.
2. Write a constraint file (.CST for F6.x, .UCF for F1.x) which
   contains the Timespecs.  This constraints file will be read
   into the Design Manager during implementation.

Refer to the Xilinx Development Systems Reference Guide for more information abo
ut using Timespecs and Timing Driven
Implementation.

**Note that this solution applies to the Metamor XVHDL compiler
only.  If using the Express HDL compiler, you have the ability
to use the Express Constraints GUI to set up timegroups and
timespecs.


Solution 1:

Example: Putting TNMs on Instantiated Instances
-----------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity DP_RAM is
   port (WR, DATA, CLK, RST: in std_logic;
	 ADDR0, ADDR1, ADDR2, ADDR3: in std_logic;
	 DPRA0, DPRA1, DPRA2, DPRA3: in std_logic;
	 DPOUT, SPOUT, DOUT: out std_logic);
end DP_RAM;

architecture INST of DP_RAM is
   component RAM16X1D
      port (D,WE,WCLK,A3,A2,A1,A0,
	    DPRA3,DPRA2,DPRA1,DPRA0: in std_logic;
	    SPO,DPO: out std_logic);
   end component;
   attribute TNM: string;
   attribute TNM of U1:  label is "RAMTNM";
begin
   U1: RAM16X1D
      port map (
	D=>DATA, WE=>WR, WCLK=>CLK,
	A3=>ADDR3, A2=>ADDR2, A1=>ADDR1, A0=>ADDR0,
	DPRA3=>DPRA3, DPRA2=>DPRA2, DPRA1=>DPRA1,
	DPRA0=>DPRA0, SPO=>SPOUT, DPO=>DPOUT);
end INST;



Solution 2:

Attaching TNM attributes in the VHDL code
-----------------------------------------

A) Inferred Components

To attach a TNM attribute to an inferred PAD, Flip-Flop or
Latch, use the following syntax:

      attribute TNM:  string;
      attribute TNM of <signal_name>:  signal is "<tnm_id>";

where <signal_name> is the Q output of the flip-flop or
latch, or the port name for the desired pad, and <tnm_id> is
the TNM identifier name which you want to assign to the
instance.

If a signal is declared as a top-level entity output or inout
port, and is also the output of a flip-flop or latch, a TNM
attribute attached to that signal will be placed onto the
OPAD, and not the flip-flop.  In order to attach a TNM
attribute to the flip-flop in this case, a dummy signal must
be created.

See the resolution titled "Example: Putting TNMs on Inferred
Instances" for example VHDL code.


B) Instantiated Components

To attach a TNM attribute to an instantiated flip-flop, RAM
or latch, use the following syntax:

      attribute TNM:  string;
      attribute TNM of <instance_name>:  label is "<tnm_id>";

where <instance_name> is the instance name assigned to the
instantiated component in the VHDL code, and <tnm_id> is the
TNM identifer name which you want to assign to the instance.

See the resolution titled "Example: Putting TNMs on
Instantiated Instances" for example VHDL code.


Writing a Constraint File with Timespecs
----------------------------------------

After attaching TNMs to the desired instances in the VHDL
file, you must write a constraint file (<project_name>.CST for
F6.x or <project_name>.UCF for F1.x) which will be read by the
Xilinx Design Manager during implementation.

Below is an example constraint file.  This constraint file
assumes that the TNMs INPAD, FLOP_X, FLOP_Y, FLOPOUT, and
OUTPAD have been defined.

##CST file for use with Foundation 6.x##
timespec="ts01=from:INPAD:to:FLOP_X=20ns";
timespec="ts02=from:FLOP_X:to:FLOP_Y=8ns";
timespec="ts03=from:FLOPOUT:to:OUTPAD=8ns";
timespec="ts04=from:FLOP_Y:to:FLOPOUT=10ns";

##UCF file for use with Foundation F1.x##
TIMESPEC TS01 = FROM : INPAD : TO : FLOP_X : 20ns;
TIMESPEC TS02 = FROM : FLOP_X : TO : FLOP_Y : 8ns;
TIMESPEC TS03 = FROM : FLOPOUT : TO : OUTPAD : 8ns;
TIMESPEC TS04 = FROM : FLOP_Y : TO : FLOPOUT : 10ns;



Solution 3:

Example: Putting TNMs on Inferred Instances
-------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FLOPS is
   port (DIN1, CLK, RESET: in std_logic;
	 DOUT1: out std_logic);
end FLOPS;

architecture USE_TSPEC of FLOPS is
   signal X : std_logic;  -- Internal flip-flops
   signal Y : std_logic;

   signal DUMMY: std_logic;  -- This lets us place a TNM on
			     -- both the flip-flop and on the
			     -- output pad DOUT1.
   attribute TNM: string;
   attribute TNM of DOUT1:  signal is "OUTPAD";
   attribute TNM of DIN1:  signal is "INPAD";
   attribute TNM of X:	signal is "FLOP_X";
   attribute TNM of Y:	signal is "FLOP_Y";
   attribute TNM of DUMMY: signal is "FLOPOUT";
begin
   process (CLK, RESET)
   begin
      if RESET='1' then
	 X <= '0';
	 Y <= '0';
	 DUMMY <= '0';
      elsif (CLK'event and CLK='1') then
	 X <= DIN1;
	 Y <= X;
	 DUMMY <= Y;
      end if;
   end process;

   DOUT1 <= DUMMY;  -- Pass the output of the last FF to the
		    -- OPAD.  This dummy signal is created to
		    -- allow us to put a TNM on the last FF
		    -- whose output is also the top-level
		    -- pad.
end USE_TSPEC;



End of Record #1487