Answers Database

PRE-M1: CONCEPT, SYNERGY, VERILOG 4000E and 5200 libraries are availablefrom Cadence ftp as patches to 9504


Record #1527

Product Family:  Software

Product Line:  Cadence

Problem Title:
PRE-M1: CONCEPT, SYNERGY, VERILOG 4000E and 5200 libraries are
availablefrom Cadence ftp as patches to 9504



Problem Description:
Keywords: 5200 4000E Concept Verilog Synergy ftp patch

Urgency: standard

General Description:
The latest Concept, Verilog and Synergy Hotfix for
the XACT flow are available on the Cadence FTP server
in the 9504 and 9604 patch areas.  These kits include XC5200
and XC4000E support.

You will need:

From ftp://ftp.cadence.com/patches/9504/pic/sun4/
-------------------------------------------------

1.   picXilFlow96.04-p005sun4.t.Z	   9/2/96
   -- New Concept Xilinx FPGADesigner UI

2.   xilNetlist96.04-p003sun4.t.Z	   8/23/96
   -- new Xilinx netlister for use with Xilinx XC5200 devices

3.   PICTools96.04-s005sun4.t.Z 	   10/29/96
   -- new Xilinx back-annotation executable for use with
      Xilinx XC5200 devices


From ftp://ftp.cadence.com/patches/9504/pic/indep/
--------------------------------------------------

4.  xilVerilogLib96.04-s002.t.Z 	 2/19/97
   -- new Xilinx Verilog library for use with Xilinx XC5200
      devices

5.  xilConceptLib96.04-p004.t.Z 	 8/23/96
   -- new Xilinx Concept library for use with Xilinx XC5200
      devices

6.  xilComposeLib96.04-s003.t.Z 	 4/23/97
   -- new Composer/Synthesis library to fix PCRs 155686,
      175631, 179802, 180474 and Synergy library for use
      with Xilinx XC5200 devices


To install these hotfixes, copy them to your Cadence root
directory, then uncompress and tar extract each one.  (If you
have sourced an appropriate Cadence setup file for your
system, you can determine what your Cadence root directory is
by typing "cds_root"):

   uncompress <archive_name>.t.Z
   tar xvf <archive_name>.t



NOTE:  these hotfixes include complete Concept, Synergy and
Verilog interface support for the 2K, 3K, 4K and 7K
architectures as well.


Also NOTE:  You should download the patch version as
specified above, or whatever later revision exists at
this same location on the Cadence ftp site.

LATER Revision = either a higher revision number (e.g., p005
instead of p004), a higher release number (e.g. 97A vs.
96.04), or an s (special) rather than a p (production).

	PICTools96.04-s002sun4.t.Z
		----- |---
		  |   | |
		  |   | +- Kit revision
		  |   +--- Kit type (prod comes before
			   special)
		  +------- Kit release number


Solution 1:

The following bugs have been fixed in this archive:


29761:	    CONCEPT2XNF "No usable extension" error from on
	    INPORT & OUTPORT in XC4000E cc8re, cc16re, cd4cle
	    counter macros

29641:	    CE pin should float to VCC on XC4000E ifdx,
	    ifdxi, ofdtx, ofdtxi, ofdx, & ofdxi


MINOR:
------

29747:	size property on XC4000E and XC4000 ifd and ofd should
	be set to 1, not "size" (fixed in XC4000E and XC4000)

29748:	size property missing on xpads_hdl IOPAD body

29755:	XC4000E/XC4000 x74_280 symbol body is missing "F"
	note/label on F pin



NO BUG Number Assigned: XNFMERGE error 220 on IFD8, OFD8, and
	OFD16 symbol bodies--"ERROR 220: Can't open file
	'ifd.xnf'."   "LEVEL" property needed to be set to
	MXILINX.   (Fixed in XC4000 and XC4000E)



Solution 2:

*** CONCEPT-only users (not using Synergy):

download patches #1, 2, 3, 4 and 5:

(picXilFlow, xilNetlist, PICTools, xilVerilogLib,
and xilConceptLib.




Solution 3:

*** COMPOSER-only and COMPOSER/SYNERGY users:

Download patches  #3, #4, and #6

(PICTools, xilVerilogLib, and xilComposeLib).

NOTE: Composer libs do not include 4000E or 5200 support.



Solution 4:

*** Verilog-only users:

a. If you are using the ES-Verilog interface,

  1) you should be using the netlisters funcnetx, timenetx,
     xnf2verilog, and xcdsprep in the ES-Verilog archive
     on the Xilinx 5.2.1 CD--this contains the latest
     version of these programs.  See (Xilinx Solution 1115).

  2) download #4, extract, and copy
     $CDS_INST_DIR/share/library/xilinx/verilog* to
     $XACT/data.

b. If you are using the Cadence Verilog interface shipped by
   Cadence and doing Verilog entry and simulation
   only, download #1, #2, #3, and #4.



End of Record #1527