Answers Database

Cadence CONCEPT, VERILOG: Interim solution for doing 9500 designs beforeM1.0 release


Record #1529

Product Family:  Software

Product Line:  Cadence

Problem Title:
Cadence CONCEPT, VERILOG: Interim solution for doing 9500 designs
beforeM1.0 release



Problem Description:
Customers looking for Cadence Concept and Verilog simulation
support for 9500 designs before the Merged 1.0 release can use
the Concept XC7000 libraries for design entry, and a specially
packaged set of XC7000 Verilog libraries for simulation.

The XC7000 Concept libraries are the same libraries shipped in the
9502/9504 Cadence release.  The XC9500/7000 Verilog library and
interface is available via ftp for both Sun4 and HP7 platforms and
information on accessing this interface is being made available by
request only.



Solution 1:

Whereas the Concept XC7000 libraries are already included in the
Concept/Xilinx interface, the XC9500/7000 archives must be downloaded from ftp.x
ilinx.com.  From Netscape, log in to ftp://ftp.xilinx.com and
navigate to the /pub/swhelp/cpld area.	Download one of these archives:

   ver9ksun.tar.Z    (Sun4 platform)
   ver9khp.tar.Z      (HP7 platform)

To extract the archive:

	     uncompress   <filename>.tar.Z
	     tar xvf   <filename>.tar

where <filename> is either "ver9ksun", or "ver9khp".


The archive contains a script called "xepldsim" that must be run
with a -verilog option to generate a Verilog netlist for a 9k
design using the 7k libraries.




End of Record #1529