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Verilog naming rules for user-specified identifiers in Xilinx designs


Record #1535

Product Family:  Software

Product Line:  Cadence

Problem Title:
Verilog naming rules for user-specified identifiers in Xilinx designs


Problem Description:
1. An identifier in Verilog is any sequence of letters, digits, dollar
signs ($), and the underscore (_) symbol.  More specifically, only the
following characters are legal in Verilog names:

      a-z, A-Z, 0-9, _, and $

2. The first character must not be a digit or $; it can be a letter or an
underscore.

3. Upper- and lowercase letters are considered to be different (unless the
upper case option is used when compiling).

4. Identifiers can be up to 1024 characters long.

Examples of valid identifiers:

shiftreg_a
busa_index
error_condition
merge_ab
_bus3
n$657
bus_a[0]

4. From the Verilog-XL Reference Manual:
Escaped identifiers start with the backslash character (\) and provide
a means of including any of the printable ASCII characters in an
identifier (the decimal values 33 through 126, or 21 through 7E in
hexadecimal). An escaped identifier ends with white space (blank, tab,
newline). Neither the leading backslash character nor the terminating
white space is considered to be part of the identifier.

The primary application of escaped identifiers is for translators from
other hardware description languages and CAE systems, where special
characters may be allowed in identifiers. Escaped identifiers should not
be used under normal circumstances.

Examples of escaped identifiers:

  \busa+index
  \-clock
  \***error-condition***
  \net1/\net2
  \(a,b)
  \a*(b+c)
  \mybus- [1]	    (bit one of bus named "mybus-".  This example
		     found by experimenting with the tools and verifying
		     the result with Cadence)

Note:  Remember to terminate escaped identifiers with white space,
otherwise characters that should follow the identifier are considered
part of the identifier itself.

5. VHDL and Verilog keywords cannot be used as identifiers.

6. If you are entering your design in Concept, user specified names
MUST start with a letter.



REFERENCES:  9604 Verilog-XL Reference Guide v2.3, Section 2.5


Solution 1:





End of Record #1535