Answers Database

ES-VERILOG/VERILOG-XL: Extraneous 4000E setup/hold violations on WCLK


Record #1541

Product Family:  Software

Product Line:  Cadence

Problem Title:
ES-VERILOG/VERILOG-XL:  Extraneous 4000E setup/hold violations on WCLK


Problem Description:
Extraneous timing violations on the WCLK pin of 4000E dual port and synchronous
RAM components may be flagged on XC4000E
Verilog netlists.  These violations may be generated by
simulation models found in versions of the BETA ES-Verilog
interface for the 4KE and 5K architectures downloaded before March 13, 1996.


Solution 1:

To fix the problem, you must use the version of the ES-Verilog
interface included on the XACTstep Core Tools v5.2.1 CD for
Sun and HP workstations, or install the 9504 release from
Cadence.

On the XACTstep Core Tools v5.2.1 CD, the archive is located
in the XBBS/SWHELP directory and contains :

a. xnf2verilog v9504-1.30v

b. revised synchronous and dual port RAM models--
ram16x1d.v, ram32x1d.v, ram16x1s.v, and ram32x1s.v
--which have a revised timing check section (1 has been
changed to -1 in the $setuphold function call argument lists
for the hold value multiplier).

c. Verilog-XL must be invoked using two special options:

    +neg_tchk and +splitsuh

so that Verilog-XL will accept the
negative delay values used in the corrected timing model.

Example:  verilog +neg_tchk +splitsuh design.v testbench.v

On the Sun4 platform, a patched version of Verilog-XL, v2.2.8
or later, is required to fix a core dump problem when the
+neg_tchk option is specified.	A configurable version of this
Verilog-XL patch may be downloaded from ftp.xilinx.com in the
pub/swhelp/cadence area (SunOS executables):

    vconfig03.23-p007sun4.t.Z
    verilogxl02.20-s018sun4.t.Z

The core dump problem when Verilog-XL is invoked with the
+neg_tchk option is specific to the Sun4 version of Verilog-XL
and was not a problem on the HP version.

The problem is also fixed in the 9504 release from
Cadence--this includes the fixed version of xnf2cds, the RAM
models, and the Verilog-XL executable.




End of Record #1541