Answers Database

VERILOG-XL: warning! Cannot annotate PORT delay to MIPD for port


Record #1555

Product Family:  Software

Product Line:  Cadence

Problem Title:
VERILOG-XL: warning! Cannot annotate PORT delay to MIPD for port


Problem Description:
Keywords:  mipd, verilog

Urgency:  standard

General description:
These warnings are flagged against the SDF file and may be caused
by a port (or external I/O) in the design being unconnected.  If the
warning is about a WCLK pin on a 4000E RAM, it may be a bug in the version
of Verilog-XL being used.

Example:

"testfixture.verilog", 438: warning! Cannot annotate PORT delay to MIPD for port
 NSDC_CCS_DATA_OUT_25_.wclk
       SDF line 1552


Solution 1:

Check to see whether the port is connected in the actual design.  If
it is not connected, the warning is valid, but does not necessarily
constitute a problem if that is the user's intention.

This Warning is seen only with versions of Verilog-XL that are
earlier than 2.2.8.  The solution is to update to at least
v2.2.8 of Verilog-XL.  The 9504 release ships with Verilog-XL v2.3.3.




Solution 2:

If the warning is about a WCLK pin on a 4000E RAM:

  SDF line 1532
 "testfixture.verilog", 438: warning! Cannot annotate PORT delay to MIPD
  for port NSDC_CCS_DATA_OUT_25_.wclk

it may be a bug if you are using pre-v2.2.8 versions of Verilog-XL.
In this case, an update to a newer version may correct the problem.



End of Record #1555