Answers Database

PCI macro: Possible simulation problem in Verilog XL due to net rename


Record #1564

Product Family:  Software

Product Line:  Logicore

Problem Title:
PCI macro: Possible simulation problem in Verilog XL due to net rename


Problem Description:
The user may run into a problem when trying to simulate the v1.0 PCI
Logicore using Verilog XL from Cadence.

The translation tools that create the Verilog simulation files
converts '/', '-', and '$' to underscores. The program that does the
conversion of these characters is called xnf2verilog and is run by
funcnetx and timenetx. The reason these characters are converted to
underscores is because they are illegal in Verilog (see related solution
record 1535 on naming rules in Verilog for Xilinx designs).

An example of the problem is:

	SYM, PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY/$1I30, DFF, HIERG=208,
		SCHNM=FDPE, TNM=PCI_FFS, INIT=S, LIBVER=2.0.0
	PIN, C, I, CK
	PIN, CE, I, PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY/$1N36
	PIN, D, I, PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY_D
	PIN, PRE, I, PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY/PRE
	PIN, Q, O, PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY-PRE
	END

Notice the names of the Q output net and the PRE input net.  When xnf2verilog
converts the /'s and -'s to _'s, the signals go from:

	PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY/PRE
	PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY-PRE

to:

	PCI_LC_PCI_CNTL_PCI_OFCN_PCI_XOE_OE_TRDY_PRE

This causes the two nets to be shorted and simulation to fail.


Solution 1:

Xilinx has fixed this problem in version 1.1 of the PCI
LogiCore module.



End of Record #1564