Answers Database

Foundation VHDL: Can I use a testbench for VHDL-file simulation?


Record #1612

Product Family:  Software

Product Line:  Aldec

Problem Title:
Foundation VHDL: Can I use a testbench for VHDL-file simulation?


Problem Description:
Can I create a VHDL testbench file in order to perform
simulation on a Foundation VHDL file?


Solution 1:

Foundation does not have a VHDL-based simulator at this time,
and therefore it cannot read a testbench file to perform
simulation.  All simulation of VHDL files must be performed
in the Foundation Logic Simulator after synthesis.

If you wish describe your simulation stimulus using a text
file, the Foundation Logic Simulator can read in a "macro"
(.CMD) file.

Information on creating and using a macro file can be found
in the online documentation for the Logic Simulator, and also
in the Documentation Update Pack, available at

ftp://ftp.xilinx.com/pub/swhelp/foundation/fnddoc1a.exe



End of Record #1612