Answers Database

M1 : Examples of Timing Specification in the User Constraint File (.ucf)


Record #1642

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1 : Examples of Timing Specification in the User Constraint File (.ucf)


Problem Description:
The Design Timing specification can be written in user
constraint file (.ucf). This is especially usefull for HDL design flow where the
 methodology becomes as easy as entering
TIMESPEC in schematic design. This solution describes key word used in the .ucf
file to define the timegroup and the timespec.



Solution 1:

Define timing group.

The first step is to define the starting and ending point
where the timing specification apply.
They are generic key words : PADS, FFS, LATCH, RAM which apply to all the pads,
ffs, latch or memory.
Specific timing group of logic can be created by using TNM,
TPTHRU TIMEGRP, FFS(instance_name), PADS(instance_name),
LATCH(instance_name), RAM(instance_name). For instance :

NET machin TNM = pipea;
#TNM=pipea is attached to the net machin

NET clk2 TNM = clk2_grp;
#TNM=clk2_grp is attached to the net clk2

INST $1I64 TNM = spdram;
#TNM=spdram is attached to the symbol which has the instance #$1I64

TIMEGRP buspads = PADS(bus*);
#The wild character * is used to define the timing group buspad
#which contains all the pads named bus something.

NET rambus0 TPTHRU = ramvia;
#TPTHRU defines an intermediate point to specify a through #point



Solution 2:

Define the Timing Specification : From To stype Timespecs.

The FROM:TO style describes the timing path from one group to another. The optio
n FROM:THRU:TO precise which path must be choice.

TIMESPEC TS01 = FROM:buspads:TO:pipea:20;
#This specification states that all paths from each member of
#the buspads group to each member of the pipea groups must be
#lower than 20 ns.

TIMESPEC TS02 = FROM:FFS:TO:RAMS = 15;
#This specification states that all paths from flip-flop to all
#RAM must be lower than 15 ns.

TIMESPEC TS03 = FROM:FFS:THRU:ramvia:TO:PAD(truc*) = 40;
#This specification states that the paths from all the #flip-flop through the in
termediate point ramvia and to the
#pads named truc something must be lower than 40 ns.



Solution 3:

Define the Timing specification : Period style Timespecs.

In addition to FROM:TO style TIMESPECS there are several others forms of Timespe
cs provided by the M1 tools :

TIMESPEC TS04 = PERIOD:clk2_grp:50;
#The clock period of the group clk2_grp is lower than 50ns.



NET clk3 PERIOD = 40ns;
#The clock period of the clock clk3 is 40ns. Note that clk3 is
#the signal name of the output of the clock buffer.

NET add0_in OFFSET=IN:14:AFTER:clk3;
#Define OFFSET of ADD0 with respect of clk3 (40ns)



End of Record #1642