Answers Database

M1 : HDL flow with LogiBLOX, implementation and simulation files.


Record #1673

Problem Title:
M1 : HDL flow with LogiBLOX, implementation and simulation files.


Problem Description:
LogiBLOX generates both implementation and simulation files for HDL flow
This solution describes this files for both VHDL and Verilog.


Solution 1:

VHDL flow :

LogiBLOX generates .ngo, .vhi, .vhd :

	VHDL Instantiation Template (.vhi) is the LogiBLOX VHDL
      component declaration/instantiation template to be copied
      into the user's VHDL design when a LogiBLOX module is to
      be instantiated. Selecting the "VHDL template" option in
      the LogiBLOX Setup dialog box will enable the generation
      of the LogiBLOX VHDL component declaration/instatiation
      template.

	 LogiBLOX Implementation Netlist (.ngo) is the
      LogiBLOX module implementation netlist in Xilinx-NGD
      binary format. The implementation netlist is used in the
      LogiBLOX HDL instantiation flow and the VHDL synthesizer
      process the instanciated module as a black box. This
      LogiBLOX-specific implementation netlist will be merged
      with the top-level design during the implementation
      process. Selecting the "NGO File" option in the LogiBLOX
      Setup dialog box will enable the output of the .ngo
      netlist.

	VHDL Simulation Model (.vhd) is ONLY the behavioral
      VHDL simulation model of LogiBLOX module behavioral VHDL
      and the synthesizer should not use it for implementation
      Selecting the "Behavioral VHDL Model" option in the
      LogiBLOX Setup dialog box will enable the generation of a
      behavioral simulation model.



Solution 2:

Verilog flow :

LogiBLOX generates .ngo, .vei, .v :

	 Verilog Instantiation Template (.vei) is the LogiBLOX
      verilog component declaration/instantiation template to
      be copied into the user's Verilog design when a LogiBLOX
      module is to be instantiated. Selecting the "Verilog
      template" option in the LogiBLOX Setup dialog box will
      enable the generation of the LogiBLOX Verilog component
      declaration/instatiation template.

	 LogiBLOX Implementation Netlist (.ngo) ž is the
      LogiBLOX module implementation netlist in Xilinx-NGD
      binary format. The implementation netlist is used in the
      LogiBLOX HDL instantiation flow and the synthesizer
      processed the instanciated module as a black box. This
      LogiBLOX-specific implementation netlist will be merged
      with the top-level design during the implementation
      process. Selecting the "NGO File" option in the LogiBLOX
      Setup dialog box will enable the output of the .ngo
      netlist.

	Verilog Simulation Model (.v) is ONLY the structural
      Verilog simulation model and the synthesizer should not
      used it for implementation. Selecting the "Structural
      Verilog Model" option in the LogiBLOX Setup dialog box
      will enable the generation of a structural simulation
      model.




End of Record #1673