Answers Database

TIMING ANALYZER 6.0.1: Discrepancy between Timing Analyzer and Xdelay


Record #1683

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
TIMING ANALYZER 6.0.1: Discrepancy between Timing Analyzer and Xdelay


Problem Description:
By default, Xdelay and Timing Analyzer trace different paths for maximum delays.


Solution 1:

Timing Analyzer and XDELAY have different default settings.
XDELAY includes Asynchornous set and reset paths, while Timing
Analyzer does not. To turn this on in the Timing Analyzer, select:

PATH FILTERS->COMMON FILTERS->CONTROL POSSIBLE FALSE PATHS
SELECT 'SET/RESET to Q PIN OF FLIP-FLOPS'
MOVE all signals to INCLUDED BLOCKS.

Timing Analyzer should now trace the same paths as XDELAY and report
the same maximum delays.



End of Record #1683