Answers Database
XC9500: Test process of devices before shipment
Record #1700
Product Family: Hardware
Product Line: 9500
Problem Title:
XC9500: Test process of devices before shipment
Problem Description:
What tests have been run to verify that 9500 devices are
functional before they are shipped?
Solution 1:
The test sequence involves the following steps:
1) Wafer sort #1
Logic functional tests, program/erase tests
(all cells left in programmed state).
After this test, the wafer is baked at a high
temperature to test for cell leakage (= charge loss).
The bake is at 250 deg C for 24 hours.
2) Wafer sort #2
Programmed cells are checked for threshold voltage
changes as a result of wafer bake. After this test,
bad devices (failing either wafer sort #1 or #2)
are marked. All good devices are sent to be packaged.
3) Final test
Full logic functional tests and full program/erase
tests. After this test, the good devices are
speed-binned, marked, and shipped.
The XC9500 devices are fully tested during "final test", which
is the stage when the packaged units return from packaging, and
just before the devices are marked and shipped. During final
test, every XC9500 device is fully tested for program/verify
(both JTAG/ISP and non-ISP modes) and logic functionality
(using both programmed cells and special test circuitry).
End of Record #1700
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |