Answers Database

7300: Fast clock driver is connected to non-fast clock pin


Record #1712

Product Family:  Hardware

Product Line:  7300

Problem Title:
7300: Fast clock driver is connected to non-fast clock pin


Problem Description:
Keywords:  Fast clock, FCLK

Urgency:  Standard

General Description:

Can I create a negative-edge triggered flip-flop by inverting
the FastClock (FCLK) signal?

ie:
IPAD -> BUFG -> INV -> Clk pin of Flip-Flop


Solution 1:

This is an illegal configuration in an XC7300 device.

FastClks go directly from the dedicated input to the clock pin of the rising-edg
e-triggered flip
flop. There is no programmable inversion feature.  So, by specifying an
inverter, the user is trying to drive the FCLK to a macrocell and-array,
there is no physical connection for this.

To create an inverted FastClk signal the user has three
choices:

1) Invert the clock signal off-chip and then bring it in
   through an IPAD and BUFG.

2) Bring the clock in through an IBUF, invert it on-chip, then
   feed it through an OBUF and finally into the BUFG.

3) Abandon the BUFG and use a regular IBUF.  In this case the
   clock will no longer be a FastClk, and thus can only clock
   flip-flops in High-Density Function Blocks.



End of Record #1712