Answers Database

vhdlan/vhdldbx:Limits of VHDL/Verilog Simulation in the Current XSI Flow


Record #1724

Product Family:  Software

Product Line:  Synopsys

Problem Title:
vhdlan/vhdldbx:Limits of VHDL/Verilog Simulation in the Current XSI Flow


Problem Description:
keywords:
XSI,Verilog-XL,simulation,functional,timing,VHDL,Verilog,VSS


urgency:
standard


General Description:

For the HDL flows with Synopsys, only


Solution 1:

In the current VHDL XSI flow, there are two types of VHDL simulation
available to customers: functional and timing.	Timing simulation
is a fully developed flow in XSI with Synopsys' VSS tool  Functional
simulation, otherwise known as pre-synthesis pre-route simulation,
is only possible with purely behaviorially code.

In the XSI software, there are essentially two different types of
libraries and XNF files.  There are 'synthesis' libraries and
'simulation' libraries.  In most cases, the library components of
the XSI synthesis library and XSI simulation libraries are identical.
A AND2 in the synthesis library is indentical to the AND2 in the
simulation library.  In the case of registers and OBUFT's, the two
XSI libraries differ.  In the XSI simulation libraries, the
registers have an extra pin called GSR.  Similarly, the OBUFT's in
the XSI simulation libraries also have an extra pin called GTS.  These
extra pins were created in the XSI simulation library to simulate
the global resources which are toggled when the FPGA/CPLD is powered up.

Functional simulation of VHDL code with instantiated registers or
instantiated OBUFT's is not possible because of the two XSI libraries.
In the XSI functional simulation flow, all VHDL files are read by
vhdlan.  But, when vhdlan reads in VHDL code with an instaniated register,
and/or an instantiated OBUFT, the library component called out is
the *synthesis* library component.  For simulation, the simulation library
component must be called out.  While it hasn't been tested thorougly,
it should be possible to functionally simulate VHDL code with
purely instantiated combinational logic, since logic in the FPGA
function generators do not have 'extra' pins.



Solution 2:

In the Xilinx Synopsys/Verilog XL flow, only timing simulation
is fully supported.  Similar to VHDL under XSI, since the
XSI synthesis libraries and Verilog XL simulation library components
have different pins(the simulation FD has a GSR while the synthesis
FD does not), true functional simulation isn't possible.

For additional details with regard to Verilog XL and functional
simulation, please see Xilinx solution 806.



End of Record #1724