Answers Database

CONCEPT2XIL: Warning! verilog.v in calc_lib.glbl is not a link - leavingit [Van-LIBSRC]


Record #1728

Product Family:  Software

Product Line:  Cadence

Problem Title:
CONCEPT2XIL: Warning! verilog.v in calc_lib.glbl is not a link -
leavingit [Van-LIBSRC]



Problem Description:
Keywords: concept2xil van glbl libsrc

Urgency: standard

General Description:

<output>
CONCEPT2XIL/VAN: "Warning! verilog.v in calc_lib.glbl is not a
link - leaving it [Van-LIBSRC]

Writing calc_lib.adsu4:hdl"
</output>

This warning from the VAN subprogram means that the VERILOG.V
netlist in the hdl/ subdirectory (or view) for the design
block (in this case, adsu4) in your

<output>
   xilinx_run_directory/<design>_lib
</output>

directory is an actual file, rather than a link, so VAN cannot
overwrite it.  VERILOG.V is usually just a writeable link to
the verilog.v file underlying the specified component in the
upper level design directory.

This is not a problem for the M1 Xilinx flow because the
verilog.v file in the <design>_lib directory is not used in
this flow.  For functional simulation, the verilog.v
underlying each schematic block in the actual design directory
is used.

This problem may be a side effect of copying design files
from one location to another with a straight "cp" command.


Solution 1:

This warning can usually be ignored.  To turn the warning off,
delete your Xilinx run directory and reprocess the design.



End of Record #1728