Answers Database

Foundation XVHDL: How to use Wide-Edge Decoders


Record #1839

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL:  How to use Wide-Edge Decoders


Problem Description:
Keywords: foundation xvhdl edge decoders

Urgency: standard

General Description:
Below is an example of how to instantiate Wide-edge Decoders
in XC4000 Foundation XVHDL (Metamor) designs.


Solution 1:

Foundation F1.3/F1.4
====================

--Example of instantiating Wide Edge Decoders.

--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;

entity edge_decoder is
   port (DATA3, DATA2, DATA1, DATA0: in std_logic;
	CLK:  in std_logic;
	IN1:  in std_logic;
	RESET: in std_logic;
	QOUT: out std_logic);
end edge_decoder;

architecture use_decode of edge_decoder is
   component DECODE4
      port ( A3, A2, A1, A0: in std_logic; O: out std_logic);
   end component;

   component PULLUP
      port (O: out std_logic);
   end component;

   signal DECOUT: std_logic;

begin
U1:  DECODE4
   port map (A3 => DATA3, A2=>DATA2, A1=>DATA1, A0=>DATA0,
	     O=>DECOUT);
U2:  PULLUP
   port map (O=>DECOUT);

process (CLK, RESET)
	begin
	   if RESET='1' then
	      QOUT <= '0';
	   elsif (CLK'event and CLK='1') then
	      if DECOUT = '1' then
		 QOUT <= IN1;
	      end if;
	   end if;
	end process;

end use_decode;




Solution 2:

Foundation 6.x
==============

--Example of instantiating Wide Edge Decoders.

--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;

entity edge_decoder is
   port (DATA3, DATA2, DATA1, DATA0: in std_logic;
	CLK:  in std_logic;
	IN1:  in std_logic;
	RESET: in std_logic;
	QOUT: out std_logic);
end edge_decoder;

architecture use_decode of edge_decoder is
   component DECODE4
      port ( A3, A2, A1, A0: in std_logic; O: out std_logic);
   end component;

   component PULLUP
      port (O: out std_logic);
   end component;

   signal DECOUT: std_logic;

begin
U1:  DECODE4
   port map (A3 => DATA3, A2=>DATA2, A1=>DATA1, A0=>DATA0,
	     O=>DECOUT);
U2:  PULLUP
   port map (O=>DECOUT);

process (CLK, RESET)
	begin
	   if RESET='1' then
	      QOUT <= '0';
	   elsif (CLK'event and CLK='1') then
	      if DECOUT = '1' then
		 QOUT <= IN1;
	      end if;
	   end if;
	end process;

end use_decode;

=============================================================

The following files must also be copied into the project
directory:

<ACTIVE>\VHDL\XLNX_LIB\XC4000\DECODE4.XNF
<ACTIVE>\VHDL\XLNX_LIB\XC4000\PULLUP.XNF

where <ACTIVE> is the install directory for the Foundation
Active-CAD software.  (Typically C:\ACTIVE)



End of Record #1839